ANXPLORER ETC2 [List of Unclassifed Manufacturers], ANXPLORER Datasheet - Page 3

• Manufacturer Part Number: ANXPLORER
• Description: EDA TOOL FOR SCHEMATIC LEVEL OPTIMIZATION OF ANALOG & RF CIRCUITS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

methodology for the synthesis of custom analog circuits”, Proc.
ICCAD 2001, pp 350-357. Shown in figure 3.
Technology: IBM 0.5um BSIM3v3 models, obtained from
http://www.mosis.org/test
Table 1: Specification and optimization for two stage OpAmp
Ultra wide-band OpAmp
Source: Advanced VLSI Design Lab, Indian Institute of Technol-
ogy, Kharagpur, shown in figure 4.
Technology: TSMC 0.18um BSIM3v3 models, obtained from
http://www.mosis.org/test
Table 2: Specification and optimization for ultra wide band
OpAmp
Missing entries in the specification column denote metrics which
were not part of the optimization objectives, but measured post
optimization.
High gain OpAmp
Source: Advanced VLSI Design Lab, Indian Institute of Technol-
ogy, Kharagpur, shown in figure 5.
Technology: TSMC 0.18um BSIM3v3 models, obtained from
http://www.mosis.org/test
Gain
Unity gain BW
Phase margin
CMRR
PSRR (Vdd)
Slew rate
Propagation delay
Area
Gain
Unity gain BW
Phase margin
ICMR
CMRR
PSRR (Vdd)
Settling time
Static power
METRIC
METRIC
≤ 24000 sq. micron
SPECIFICATION
SPECIFICATION
≥ 52 degrees
≥ 50 degrees
≥ 255 MHz
≥ 250 V/us
≤ 50 mW
≥ 2 GHz
≥ 68 dB
≥ 55 dB
≥ 80 dB
≥ 60 dB
≤ 2 ns
-
-
-
-
6000 sq. micron
56 degrees
55 degrees
0.4 - 1.5 V
2.18 GHz
697 MHz
403 V/us
72.6 dB
56.2 dB
86.5 dB
67.5 dB
RESULT
1.13 ns
RESULT
46 mW
86 dB
83 dB
3 ns
Figure 3: Two stage OpAmp schematic
Figure 5: High gain OpAmp schematic, with gain-booster stage
shown as a block.
VinN
VinN
Figure 4: Ultra wide-band OpAmp schematic
M7
M7
M5
M5
M3
M3
node2
node2
node6
node6
M1
M1
node4
node4
M0
M0
node0
node0
bias
bias
node7
node7
- +
- +
- +
- +
+ -
+ -
+ -
+ -
node3
node3
nbiias
M2
M2
Vdd
Vdd
M8
M8
M6
M6
M4
M4
node5
node5
node1
node1
gnd
gnd
VinP
VinP
Rz
Rz
Cc
M10
M10
M9
Vout
Vout