PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 14

• Manufacturer Part Number: PPC405EX-NPAFFFTX
• Description: PowerPC 405EX Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

PPC405EX – PowerPC 405EX Embedded Processor
General Purpose I/O (GPIO) Controller
The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single
package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by
register bit settings controlled by software. This significantly reduces the number of package pins needed to
support multiple I/O groups.
Features include:
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the PPC405 processor.
Features include:
Gigabit Ethernet
The Ethernet support provides two Gigabit (10/100/1000 Mbps) interfaces (GMII/RGMII ).
Features include:
14
• Up to 32 GPIOs available
• Direct control of all functions from registers programmed by means of OPB bus master accesses
• Time multiplexing of controller outputs to module outputs
• Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs
• Time multiplexing of module inputs to controller inputs
• Ten external interrupt sources supported
• Generate interrupt on level (high or low) or edge (rising or falling)
• Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive
• Each interrupt source/bit programmable as critical or non critical
• DCR bus interface is 32 bits wide
• Optional interrupt handler vector generation
• Programmable polarity for all interrupt types
• Interrupts of the same type do not need to be in contiguous bit positions
• Status registers provide: current state of all interrupts, current state of enabled interrupts
• ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant
• Half-duplex and full-duplex supported
• Receive FIFOs are 512 bytes with programmable thresholds
• FCS control for transmit/receive packets
• Multiple packet handling in transmit and receive FIFOs
• Unicast, multicast, broadcast, and promiscuous address filtering
• Two 256-bit hash filters for unicast and multicast frames
• Automatic retransmission of collided frames
• Runt frame rejection
• Programmable inter-frame gap
• IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame
• Wake-on-LAN and Power-over-Internet supported
externally)
triggering)
transmitting)
– GPIOs are multiplexed with alternate functions
– If not in use for dedicated functions, I/Os are available as GPIOs
– Programmable vector base address
– Programmable vector offset size
– Programmable interrupt priority ordering
Preliminary Data Sheet
Revision 1.09 - August 21, 2007
AMCC Proprietary