ACE24C16ADPTH ACE [ACE Technology Co., LTD.], ACE24C16ADPTH Datasheet - Page 8
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ACE24C16ADPTH
Manufacturer Part Number
ACE24C16ADPTH
Description
Two-wire Serial EEPROM
Manufacturer
ACE [ACE Technology Co., LTD.]
Datasheet
1.ACE24C16ADPTH.pdf
(15 pages)
Device Addressing
enable the chip for a read or write operation (refer to Figure 7).
significant bits as shown. This is common to all the EEPROM devices.
address which follows.
this bit is high and a write operation is initiated if this bit is low.
chip will return to a standby state.
Write Operations
Byte Write
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a
zero and the addressing device, such as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally timed write cycle, t
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete (refer to Figure 8).
Page Write
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the
first data word, the microcontroller can transmit up to seven more data words. The EEPROM will
respond with a zero after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (refer to Figure 9).
word. The higher data word address bits are not incremented, retaining the memory page row location.
When the word address, internally generated, reaches the page boundary, the following byte is placed
at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the
data word address will “roll over” and previous data will be overwritten.
Acknowledge Polling
polling can be initiated. This involves sending a start condition followed by the device address word.
The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
The 16K EEPROM devices all require an 8-bit device address word following a start condition to
The device address word consists of a mandatory one, zero sequence for the first four most
The next 3 bits used for memory page addressing and are the most significant bits of the data word
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the
A write operation requires an 8-bit data word address following the device address word and
The 16 devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
The data word address lower three bits are internally incremented following the receipt of each data
Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge
Technology
Two-wire Serial EEPROM
ACE24C16A
WR,
to the nonvolatile
VER 1.2
8