M391T6453FGZ3-CE6/D5/CC SAMSUNG [Samsung semiconductor], M391T6453FGZ3-CE6/D5/CC Datasheet
M391T6453FGZ3-CE6/D5/CC
Related parts for M391T6453FGZ3-CE6/D5/CC
M391T6453FGZ3-CE6/D5/CC Summary of contents
Page 1
... Unbuffered DIMMs DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 256Mb F-die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
Page 2
... Package: 60ball FBGA - 32Mx8 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization 32Mx8(256Mb) based Module Density Organization Component Composition x64 Non ECC ...
Page 3
... DQ18 150 DQ23 Connect, RFU = Reserved for Future Use 1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Front Pin Back Pin Front ...
Page 4
... DQ23 Connect, RFU = Reserved for Future Use 1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Pin Description Pin Name Description A0-A12 ...
Page 5
... Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied Supply DD SS these modules. DQS0-DQS8 Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the In/Out DQS0-DQS8 DRAMs and DQ8-17 connect to the UDQS pin of the DRAM ...
Page 6
... Unbuffered DIMMs Functional Block Diagram: 256MB, 32Mx64 Module S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 I/O 6 DQ15 I/O 7 DQS2 ...
Page 7
... Unbuffered DIMMs Functional Block Diagram: 256MB, 32Mx72 ECC Module S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 I/O 6 DQ15 ...
Page 8
... Unbuffered DIMMs Functional Block Diagram: 512B, 64Mx64 Module S1 S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 I/O 6 DQ15 ...
Page 9
... Unbuffered DIMMs Functional Block Diagram: 512MB, 64Mx72 ECC Module S1 S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 D0 I/O 1 DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 ...
Page 10
Unbuffered DIMMs Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL ...
Page 11
Unbuffered DIMMs Operating Temperature Condition Symbol TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
Page 12
Unbuffered DIMMs IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); ...
Page 13
... IDD2N IDD3P-F IDD3P-S IDD3N 1,200 IDD4W 2,280 IDD4R 2,080 IDD5B 1,960 IDD6 Normal IDD7 2,720 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap VDD= 1.9V (DDR2-533@CL=4) 840 800 920 880 64 64 ...
Page 14
... IDD3P-S 270 IDD3N 1,350 IDD4W 2,565 IDD4R 2,340 IDD5B 2,205 IDD6 Normal 90 IDD7 3,060 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap VDD= 1.9V (DDR2-533@CL=4) 945 900 990 72 72 270 225 ...
Page 15
Unbuffered DIMMs Input/Output Capacitance (V Parameter Non-ECC Input capacitance, CK and CK Input capacitance, CKE and CS Input capacitance, Addr,RAS,CAS,WE Input/output capacitance, DQ, DM, DQS, DQS ECC Input capacitance, CK and CK Input capacitance, CKE and CS Input ...
Page 16
Unbuffered DIMMs Electrical Characteristics & AC Timing for DDR2-667/533/400 SDRAM (0 °C < T < 95 °C; V CASE DDQ Refresh Parameters by Device Density Parameter Refresh to active/Refresh command time Average periodic refresh interval Speed Bins and ...
Page 17
Unbuffered DIMMs Parameter DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time ...
Page 18
... Unbuffered DIMMs Physical Dimensions: 32Mbx8 based 32Mx64/x72 Module(1 Rank) M378T3253FG(Z)3 / M391T3253FG(Z)3 M378T3253FG(Z)0 / M391T3253FG(Z)0 (2) 2.50 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 32M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T56083QF 133.35 131.35 128.95 N/A (for x64) SPD ECC (for x72 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail B DDR2 SDRAM Units : Millimeters 30 ...
Page 19
... Unbuffered DIMMs Physical Dimensions: 32Mbx8 based 64Mx64/x72 Module(2 Ranks) M378T6453FG(Z)3 / M391T6453FG(Z)3 M378T6453FG(Z)0 / M391T6453FG(Z)0 (2) 2.50 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 32M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T56083QF 133.35 131.35 128.95 N/A (for x64) SPD ECC (for x72 55.00 N/A (for x64) ECC (for x72) 4 ...
Page 20
Unbuffered DIMMs Revision History Revision 1.0 (Jan. 2004) - Initial Release Revision 1.1 (Jun. 2004) - Added lead-free part number in the ordering information - Changed IDD2P Revision 1.2 (Jan. 2005) - Revised tIH value of 667 speed ...