M391T2953BG0-CC SAMSUNG [Samsung semiconductor], M391T2953BG0-CC Datasheet - Page 18
![no-image](/images/no-image-200.jpg)
M391T2953BG0-CC
Manufacturer Part Number
M391T2953BG0-CC
Description
DDR2 Unbuffered SDRAM MODULE
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.M391T2953BG0-CC.pdf
(23 pages)
256MB,512MB,1GB Unbuffered DIMMs
Control & Address input
pulse width for each input
DQ and DM input pulse
width for each input
Data-out high-impedance
time from CK/CK
DQS low-impedance time
from CK/CK
DQ low-impedance time
from CK/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
DQ/DQS output hold time
from DQS
Write command to first DQS
latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK
setup time
DQS falling edge hold time from
CK
Mode register set command
cycle time
Write postamble
Write preamble
Address and control input
hold time
Address and control input
setup time
Read preamble
Read postamble
Active to active command
period for 1KB page size
products
Active to active command
period for 2KB page size
products
Four Activate Window for
1KB page size products
Four Activate Window for
2KB page size products
CAS to CAS command
delay
Parameter
Symbol
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
tIS
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tHP - tQHS
2* tACmin
WL-0.25
tAC min
min
0.35
0.35
37.5
0.35
375
250
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
10
50
x
2
2
x
x
DDR2-533
tAC max
WL+0.25
tAC max
tAC max
max
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
tHP - tQHS
2* tACmin
WL-0.25
tAC min
min
0.35
0.35
0.35
37.5
0.35
475
350
0.6
0.2
0.2
0.4
0.9
0.4
7.5
10
50
2
2
x
x
x
DDR2-400
WL+0.25
tAC max
tAC max
tAC max
max
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
Notes
Rev. 1.2 Jan. 2005
DDR2 SDRAM