M470L1624FT0-CA2 SAMSUNG [Samsung semiconductor], M470L1624FT0-CA2 Datasheet - Page 8

• Manufacturer Part Number: M470L1624FT0-CA2
• Description: DDR SDRAM SODIMM
• Manufacturer: SAMSUNG [Samsung semiconductor]

128MB, 256MB SODIMM
Notes 1. Includes ± 25mV margin for DC offset on V
Absolute Maximum Ratings
Note :
Recommended operating conditions(Voltage referenced to V
Power & DC Operating Conditions (SSTL_2 In/Out)
Voltage on any pin relative to Vss
Voltage on V
Voltage on V
Storage temperature
Power dissipation
Short circuit current
Supply voltage(for device with a nominal V
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
Output leakage current
Output High Current(Normal strengh driver) ;V
V
Output High Current(Normal strengh driver) ;V
V
Output High Current(Half strengh driver) ;V
+ 0.45V
TT
TT
+ 0.84V
- 0.84V
2.V
3. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
TO V
V
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
TT
REF
ID
is not applied directly to the device. V
is the magnitude of the difference between the input level on CK and the input level on CK.
, and must track variations in the DC level of V
DD
DDQ
REF
Parameter
supply relative to Vss
, both of which may result in V
supply relative to Vss
Parameter
DD
OUT
REF
of 2.5V)
OUT
OUT
= V
TT
noise. V
REF
is a system supply for signal termination resistors, is expected to be set equal to
=
TT
=
V
, and a combined total of ± 50mV margin for all AC noise and DC offset on V
Symbol
IN
V
T
V
, V
I
P
DDQ
STG
OS
DD
REF
D
REF
SS
OUT
Symbol
VI(Ratio)
V
V
V
V
=0V, T
V
V
IH
IN
ID
IL
V
should be de-coupled with an inductance of ≤ 3nH.
V
I
I
I
I
DDQ
REF
(DC)
OZ
OH
OH
(DC)
(DC)
(DC)
OL
DD
I
TT
I
A
=0 to 70°C)
0.49*VDDQ
V
V
REF
REF
-16.8
Min
0.36
0.71
16.8
-0.3
-0.3
2.3
2.3
-2
-5
-9
+0.15
-0.04
1.5 * # of component
-55 ~ +150
-0.5 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
Value
50
0.51*VDDQ
V
V
V
V
V
REF
REF
REF
DDQ
DDQ
DDQ
Max
2.7
2.7
1.4
2
5
+0.04
-0.15
and internal DRAM noise coupled
Rev. 1.2 March 2004
+0.3
+0.3
+0.6
DDR SDRAM
Unit
mA
mA
mA
uA
uA
V
V
V
V
V
V
V
-
Unit
mA
°C
W
V
V
V
Note
5
5
1
2
3
4
REF
,