M393T2950CZ3-CD5 SAMSUNG [Samsung semiconductor], M393T2950CZ3-CD5 Datasheet - Page 16

• Manufacturer Part Number: M393T2950CZ3-CD5
• Description: DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb C-die 72-bit ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

512MB, 1GB, 2GB Registered DIMMs
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB
page size products
Active to active command period for 2KB
page size products
Four Activate Window for 1KB page size
products
Four Activate Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Parameter
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tXSNR
tXSRD
tXP
tXARD
tXARDS
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
Symbol
tRFC + 10
tAC(min)+
tAC(min)+
WR+tRP
tAC(min)
tAC(min)
tIS+tCK
8 - AL
min
0.35
0.35
+tIH
250
175
200
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
2.5
10
35
45
7.5
15
2
2
3
2
2
2
3
8
0
2
2
DDR2-800
tAC(max)
tAC(max)
tAC(max)
tAC(max)
2.5tCK +
2tCK +
max
+ 0.7
+ 0.6
0.6
1.1
0.6
2.5
+1
+1
12
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
tAC(min)+
tAC(min)+
WR+tRP
tAC(min)
tAC(min)
tIS+tCK
7 - AL
min
0.35
0.35
0.35
37.5
+tIH
275
200
200
0.2
0.2
0.4
0.9
0.4
7.5
7.5
2.5
10
50
7.5
15
2
2
3
2
2
2
3
8
0
DDR2-667
2
2
2tCK+tAC
2.5tCK+tA
C(max)+1
tAC(max)
tAC(max)
(max)+1
max
+ 0.6
+0.7
0.6
1.1
0.6
2.5
12
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
tAC(min)+
tAC(min)+
WR+tRP
tAC(min)
tAC(min)
tIS+tCK
6 - AL
min
0.35
0.35
37.5
+tIH
375
250
200
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
2.5
10
50
15
3
2
2
2
2
2
2
3
8
0
2
DDR2-533
2tCK+tAC
tAC(max)
tAC(max)
tAC(max)+
(max)+1
2.5tCK+
max
0.6
1.1
0.6
2.5
+1
0.6
+1
12
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
tAC(min)+
tAC(min)+
WR+tRP
tAC(min)
tAC(min)
tIS+tCK
6 - AL
min
0.35
0.35
37.5
+tIH
0.35
475
350
200
0.2
0.2
0.4
0.9
0.4
7.5
7.5
2.5
10
50
15
10
2
2
2
3
2
2
2
3
8
0
DDR2-400
2
Rev. 1.2 Aug. 2005
DDR2 SDRAM
2tCK+tAC
tAC(max)
tAC(max)+
tAC(max)
(max)+1
2.5tCK+
max
0.6
1.1
0.6
2.5
0.6
+1
+1
12
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
tCK
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes