M368L3223ETM-CLCC4 SAMSUNG [Samsung semiconductor], M368L3223ETM-CLCC4 Datasheet - Page 16

• Manufacturer Part Number: M368L3223ETM-CLCC4
• Description: DDR SDRAM Unbuffered Module
• Manufacturer: SAMSUNG [Samsung semiconductor]

256MB, 512MB Unbuffered DIMM
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
tions through the DC region must be monotony.
Rev. 1.3 August. 2003
DDR SDRAM