M368L1624DTL-CLA2 SAMSUNG [Samsung semiconductor], M368L1624DTL-CLA2 Datasheet - Page 6

• Manufacturer Part Number: M368L1624DTL-CLA2
• Description: 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16
• Manufacturer: SAMSUNG [Samsung semiconductor]

DDR SDRAM module IDD spec table
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
AC OPERATING TEST CONDITIONS
M368L1624DTL
AC Operating Conditions
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
IDD6
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Symbol
IDD4W
IDD2Q
IDD3N
IDD4R
IDD2P
IDD2F
IDD3P
IDD7A
IDD0
IDD1
IDD5
Low power
Normal
IH
/V
Parameter/Condition
IX
IL
is expected to equal 0.5*V
Parameter
)
B3(DDR333@CL=2.5)
1400
360
500
100
140
220
800
760
720
12
80
12
6
DDQ
(V
184pin Unbuffered DDR SDRAM MODULE
DD
of the transmitting device and must track variations in the DC level of the same.
A2(DDR266@CL=2)
=2.5V, V
1200
320
460
120
180
680
620
660
12
80
72
12
6
Symbol
VIH(AC)
VID(AC)
VIX(AC)
VIL(AC)
DDQ
=2.5V, T
V
REF
See Load Circuit
+0.3 1/V
0.5*VDDQ-0.2
0.5 * V
VREF + 0.31
Value
V
A
B0(DDR266@CL=2.5)
1.5
V
= 0 to 70
REF
Min
0.7
tt
DDQ
REF
-0.3 1
1200
320
460
120
180
680
620
660
12
80
72
12
6
C
)
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
Max
Rev. 0.1 May. 2002
Unit
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
Unit
V
V
V
V
Optional
Notes
Note
Note
3
3
1
2