K9F1208B0B SAMSUNG [Samsung semiconductor], K9F1208B0B Datasheet - Page 31

• Manufacturer Part Number: K9F1208B0B
• Description: 64M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1208R0B
K9F1208B0B
K9F1208U0B
Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.
Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 15µs(t
output of R/B pin. CE must be held low while in busy for K9F1208U0B-YXB0 or K9F1208U0B-VXB0, while CE is don’t-care with
K9F1208X0B-GXB0 or K9F1208X0B-JXB0. If CE goes high before the device returns to Ready, the random read operation is inter-
rupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not output valid
data. Once the data in a page is loaded into the registers, they may be read out in 50ns(K9F1208R0B : 60ns) cycle time by sequen-
tially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last col-
umn address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
to 527 bytes may be selectively accessed by writing the Read2 command. Addresses A
area while addresses A
ures 7 to 10 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F1208X0B-Y,P or K9F1208U0B-V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read
operation.
4
to A
7
are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Fig-
R
). The system controller can detect the completion of this data transfer(tR) by analyzing the
31
0
to A
3
set the starting address of the spare
FLASH MEMORY
Preliminary