54F194DM NSC [National Semiconductor], 54F194DM Datasheet - Page 2

• Manufacturer Part Number: 54F194DM
• Description: 4-Bit Bidirectional Universal Shift Register
• Manufacturer: NSC [National Semiconductor]

Unit Loading Fan Out
Functional Description
The ’F194 contains four edge-triggered D flip-flops and the
necessary interstage logic to synchronously perform shift
right shift left parallel load and hold operations Signals
applied to the Select (S
operation as shown in the Mode Select Table Signals on
the Select Parallel data (P
H (h)
L (l)
p
X
Logic Diagram
Reset
Hold
Shift Left
Shift Right
Parallel Load
n
Names
S
P
D
D
CP
MR
Q
e
Operating
(q
0
0
SR
SL
0
Pin
e
n
–P
Immaterial
–Q
Mode
e
)
S
Low Voltage Level
e
1
3
High Voltage Level
3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition
Mode Control Inputs
Parallel Data Inputs
Serial Data Input (Shift Right)
Serial Data Input (Shift Left)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Parallel Outputs
MR
H
H
H
H
H
H
L
0
0
S
–P
1
) inputs determine the type of
Description
3
) and Serial data (D
S
X
h
h
h
l
l
l
1
S
X
h
h
h
l
l
l
0
Inputs
SR
Mode Select Table
D
D
SL
X
X
X
X
h
X
SR
l
)
2
HIGH LOW
50 33 3
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
U L
inputs can change when the clock is in either state provid-
ed only that the recommended setup and hold times with
respect to the clock rising edge are observed A LOW sig-
nal on Master Reset (MR) overrides all other inputs and
forces the outputs LOW
D
X
X
h
X
X
X
SL
l
54F 74F
20 A
20 A
20 A
20 A
20 A
20 A
Output I
b
P
p
Input I
X
X
X
X
X
X
n
n
1 mA 20 mA
b
b
b
b
b
b
IH
OH
0 6 mA
0 6 mA
0 6 mA
0 6 mA
0 6 mA
0 6 mA
I
Q
q
q
q
p
IL
H
I
L
L
OL
0
1
1
0
0
Q
q
q
q
q
q
p
L
1
2
2
0
0
1
1
Outputs
Q
q
q
q
q
q
p
L
2
3
3
1
1
2
2
TL F 9498– 4
Q
q
q
q
p
H
L
L
3
2
2
3
3