W86L488AY WINBOND [Winbond], W86L488AY Datasheet - Page 24
![no-image](/images/no-image-200.jpg)
W86L488AY
Manufacturer Part Number
W86L488AY
Description
SD/ SDIO/ MMC MEMORY CARD BRIDGE
Manufacturer
WINBOND [Winbond]
Datasheet
1.W86L488AY.pdf
(45 pages)
- Current page: 24 of 45
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Host Interface Type 2:
The Host interface type 2 is selected when XTYP2 pin is high. The data size of the CPU data bus may
be 16-bit or 8-bit and the access cycle may be in 3-cycle or 2-cycle. Figure 7-5 shows the timing of
CPU read write in type 2 and the access cycle is 3-cycle access, figure 7-6 shows the timing of CPU
read write in type 2 and the access cycle is 2-cycle access.
A[3:1]
D[15:0]
XRDYN
XBE[1:0]
A[3:1]
D[15:0]
XRDYN
XBE[1:0]
HCKI
XCSN
XASN
XRW N
HCKI
XCSN
XASN
XRWN
Fig. 7-6 Read and Write Timing in Host I/F Type 2, 2-Cycle Access.
Fig. 7-5 Read and Write Timing in H ost I/F T ype 2, 3-Cycle A ccess.
Read cycle
Read cycle
DO[15:0]
DO[15:0]
- 21 -
Publication Release Date: February 5, 2004
Preliminary W86L488
Write cycle
Write cycle
DI[15:0]
DI[15:0]
Revision 0.82
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