K4H560438D-NC SAMSUNG [Samsung semiconductor], K4H560438D-NC Datasheet
K4H560438D-NC
Related parts for K4H560438D-NC
K4H560438D-NC Summary of contents
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... Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 54pin sTSOP II package ORDERING INFORMATION Part No. K4H560438D-NC/LB3 K4H560438D-NC/LA2 K4H560438D-NC/LB0 K4H560438D-NC/LA0 K4H560838D-NC/LB3 K4H560838D-NC/LA2 K4H560838D-NC/LB0 K4H560838D-NC/LA0 Operating Frequencies - B3(DDR333) Speed @CL2 133MHz Speed @CL2 ...
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... Row Address 17 A0-A12 18 19 Auto Precharge 20 A10 256Mb package Pinout Organization Column Address 64Mx4 A0-A9, A11 32Mx8 Column address configuration - 2 - DDR SDRAM VSS VSS 54 NC DQ7 53 52 VSSQ DQ3 DQ6 VDDQ VDDQ 50 NC DQ5 49 VSSQ ...
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... LRAS LCBR CK, CK CKE 4 CK, CK Data Input Register Serial to parallel 8 8Mx8 8Mx8 8Mx8 8Mx8 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS DDR SDRAM DQi CK Rev.0.0 May. ’ 02 Data Strobe ...
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... LRAS LCBR CK, CK CKE 8 CK, CK Data Input Register Serial to parallel 16 4Mx16 4Mx16 4Mx16 4Mx16 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS DDR SDRAM DQi CK Rev.0.0 May. ’ 02 Data Strobe ...
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... Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. No Connect : No internal electrical connection is present. DQ Power Supply : +2.5V ± 0.2V. DQ Ground. Power Supply : +2.5V ± 0.2V (device specific). Ground. SSTL_2 reference voltage DDR SDRAM Rev.0.0 May. ’ 02 ...
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... Burst stop command is valid at every burst length sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 ...
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... Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560438D is 268,435,456 bits of double data rate synchronous DRAM organized 16,777,216 words by 4 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... VID(AC) VIX(AC) of the transmitting device and must track variations in the DC level of the same. DDQ Parameter - 8 - DDR SDRAM 50mV margin for all AC noise and DC offset on and internal DRAM noise REF (V =2.7V Unit K4H560438D-NC/LA0 (DDR200 100 110 150 3 1.5 ...
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... K4H560438D AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2 ...
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... K4H560438D Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time ...
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... K4H560438D 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 This derating table is used to increase t is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V ...
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... K4H560438D AC Operating Test Conditions Parameter Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate (for imput only) Input slew rate (I/O pins) Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition ...
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... Banks Double Data Rate SDRAM GENERAL DESCRIPTION The K4H560838D is 268,435,456 bits of double data rate synchronous DRAM organized 8,388,608 words by 8 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... K4H560838D Notes 1. Includes 25mV margin for DC offset bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes coupled both of which may result in V REF not applied directly to the device and must track variations in the DC level ...
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... DDR SDRAM -NC/LB0 -NC/LA0 (DDR266B) (DDR200) Max Min Max Min Max 120K 45 120K 48 120K 7.5 12 0.55 0.45 0.55 0.45 0.55 0.55 0.45 0.55 0.45 0.55 +0.75 -0.75 +0.75 -0.8 +0.8 +0.75 -0 ...
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... Input setup/hold slew rate IS IH tDS tDH (ps) (ps +75 +75 +150 +150 /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate DDR SDRAM -NC/LB0 -NC/LA0 (DDR266B) (DDR200) Max Min Max Min 15 16 0.5 0.6 0.5 0.6 2.2 2.5 1. ...
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... DQ and DQS slew rates differ. The Delta Rise/Fall Rate tDSS/tDSH tAC/tDQSCK (ps) (ps) (ps +50 +50 +50 +100 +100 - 17 - 310mV for a duration of tLZ(min) tHZ(max) (ps) (ps -50 +50 -100 +100 Rev.0.0 May. ’ 02 DDR SDRAM ...
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... REF V REF V tt See Load Circuit V =0.5*V tt DDQ R =50 T Z0=50 V REF =0.5*V DDQ C =30pF LOAD Output Load Circuit (SSTL_2) Symbol Min CIN1 2 CIN2 2 COUT 4.0 CIN3 4 DDR SDRAM Unit V DDQ V V/ns V/ns -0.31 V REF V V Max Delta Cap(max) 3.0 0.5 3.0 0.25 5.0 0.5 5.0 Rev.0.0 May. ’ 02 Note Unit ...