K4S51163LF-YPC/L/F1H SAMSUNG [Samsung semiconductor], K4S51163LF-YPC/L/F1H Datasheet

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K4S51163LF-YPC/L/F1H

Manufacturer Part Number
K4S51163LF-YPC/L/F1H
Description
8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K4S51153LF - Y(P)C/L/F
8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
FEATURES
• VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation.
• Special Function Support.
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 2 /CS Support.
• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).
ORDERING INFORMATION
- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Address configuration
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
clock.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
K4S51163LF-Y(P)C/L/F1H
K4S51163LF-Y(P)C/L/F75
K4S51163LF-Y(P)C/L/F1L
Organization
Part No.
32M x16
111MHz(CL=3)*1, 83MHz(CL2)
133MHz(CL3), 111MHz(CL2)
BA0,BA1
Bank
111MHz(CL2)
Max Freq.
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
1
The K4S51153LF is 536,870,912 bits synchronous high data
A0 - A12
Row
Interface
LVCMOS
Mobile SDRAM
Column Address
September 2004
A0 - A8
54 FBGA Pb
(Pb Free)
Package

Related parts for K4S51163LF-YPC/L/F1H

K4S51163LF-YPC/L/F1H Summary of contents

Page 1

... ORDERING INFORMATION Part No. K4S51163LF-Y(P)C/L/F75 K4S51163LF-Y(P)C/L/F1H K4S51163LF-Y(P)C/L/F1L - Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. ...

Page 2

... K4S51153LF - Y(P)C/L/F FUNCTIONAL BLOCK DIAGRAM CLK, /CAS, /RAS, /WE, DQM, CKE /CS1 /CS0 Mobile SDRAM 16Mx16 16Mx16 DQ0~DQ15 A0~A12, BA0, BA1 2 September 2004 ...

Page 3

... CAS WE L(U)DQM DDQ Symbol Mobile SDRAM *2 < Top View > 54Ball(6x9) FBGA DQ15 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ11 VSSQ VDDQ DQ4 DQ3 DQ9 VDDQ VSSQ ...

Page 4

... DDQ DDQ -0 -0.2 - DDQ - - -2 - =0.9V ± 50 mV) REF Symbol Min C 3.0 CLK 3.0 ADD C 6.0 OUT 4 Mobile SDRAM Value Unit -1.0 ~ 3.6 V -1.0 ~ 3.6 V °C -55 ~ +150 1 Max Unit Note 2.7 V 2 -0.1mA OH 0 0.1mA Max Unit Note 6 ...

Page 5

... CLK ≤ ∞ (max Page burst 4Banks Activated t = 2CLKs CCD ≥ t (min Internal TCSR Full Array -F 1/2 of Full Array 1/4 of Full Array 5 Mobile SDRAM Version Unit Note -75 -1H - 1 110 ...

Page 6

... Figure 1. DC Output Load Circuit = 2.5V ± 0.2V -25 to 70° Value 0 0.2 DDQ 0 DDQ tr/tf = 1/1 0 DDQ See Figure 2 - 0.2V, IOH = -0.1mA DDQ Output Z0=50Ω Figure 2. AC Output Load Circuit 6 Mobile SDRAM Unit Vtt=0.5 x VDDQ 50Ω 30pF September 2004 ...

Page 7

... RAS t (max) 100 RAS t (min (min) 2 RDL t (min) tRDL + tRP DAL t (min) 1 CDL t (min) 1 BDL t (min) 1 CCD Mobile SDRAM Unit Note - CLK CLK 2 CLK 2 CLK September 2004 ...

Page 8

... 5.4 7 SAC SAC SAC t 2.5 2 2.5 2 2.5 3 2.5 3 2.0 2 1.0 1 SLZ 5 SHZ - - 8 Mobile SDRAM -1L Unit Note Min Max 9.0 1000 1 2 2.5 2 September 2004 ...

Page 9

... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...

Page 10

... EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength) Mode Select BA1 BA0 Mode 0 0 Normal MRS 0 1 Reserved 1 0 EMRS for Mobile SDRAM 1 1 Reserved Reserved Address A12~A10/ NOTES: 1. RFU(Reserved for future use) should stay "0" during MRS cycle. ...

Page 11

... K4S51153LF - Y(P)C/L/F Partial Array Self Refresh 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array. BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA1=1 BA0=0 BA0=1 - Full Array Temperature Compensated Self Refresh 1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 40 ° ...

Page 12

... Mobile SDRAM Interleave Interleave ...

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