K4T56163QI-ZCLCC SAMSUNG [Samsung semiconductor], K4T56163QI-ZCLCC Datasheet - Page 24
K4T56163QI-ZCLCC
Manufacturer Part Number
K4T56163QI-ZCLCC
Description
256Mb I-die DDR2 SDRAM Specification
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K4T56163QI-ZCLCC.pdf
(42 pages)
- Current page: 24 of 42
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K4T56163QI
DQS
Note1
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
V
V
V
V
Setup Slew Rate
V
V
IL(dc)
IL(ac)
Falling Signal
REF(dc)
DDQ
IH(dc)
IH(ac)
Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS)
max
max
V
V
V
V
V
V
V
min
min
DDQ
IH(ac)
IH(dc)
IL(dc)
IL(ac)
SS
V
REF(dc)
SS
max
max
min
min
VREF to ac
region
=
V
∆TF
REF(dc)
∆TF
- Vil(ac)max
nominal slew
tDS
rate
24 of 42
tDH
Setup Slew Rate
Rising Signal
∆TR
tDS
nominal
slew rate
=
Vih(ac)min - V
tDH
VREF to ac
∆TR
region
REF(dc)
Rev. 1.0 October 2007
DDR2 SDRAM
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