K4D263238M-QC45 SAMSUNG [Samsung semiconductor], K4D263238M-QC45 Datasheet - Page 13
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K4D263238M-QC45
Manufacturer Part Number
K4D263238M-QC45
Description
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K4D263238M-QC45.pdf
(19 pages)
K4D263238M
AC OPERATING TEST CONDITIONS
CAPACITANCE
Recommended decoupling capacitance added to power line at board.
Note :
DECOUPLING CAPACITANCE GUIDE LINE
Decoupling Capacitance between V
Decoupling Capacitance between V
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input capacitance( CK, CK )
Input capacitance(A
Input capacitance
( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ
Input capacitance(DM0 ~ DM3)
1. V
2. V
All V
All V
DD
SS
Parameter
and V
and V
DD
SS
pins are connected in chip. All V
pins are connected in chip. All V
IH
SSQ
DDQ
/V
0
Parameter
IL
pins are separated each other
~A
Parameter
pins are separated each other.
)
(V
10
DD
, BA
Output
=2.5V, T
0
~BA
DD
DDQ
1
)
and V
A
and V
= 25 C, f=1MHz)
0
~DQ
SS
SSQ
SSQ
DDQ
31
)
pins are connected in chip.
pins are connected in chip.
(Fig. 1) Output Load Circuit
Z0=50
(
V
DD
- 13 -
/ V
C
Symbol
LOAD
C
DDQ
C
C
C
C
OUT
IN1
IN2
IN3
IN4
V
=30pF
=2.5V+ 5% ,
REF
Symbol
C
C
+0.35/V
0.50*V
See Fig.1
DC1
DC2
Value
V
V
1.5
1.0
V
tt
REF
=0.5*V
tt
R
DDQ
T
REF
T
=50
A
Min
1.0
1.0
1.0
1.0
1.0
= 0 to 65 C)
-0.35
DDQ
V
=0.5*V
REF
0.1 + 0.01
0.1 + 0.01
128M DDR SDRAM
Value
DDQ
Max
5.0
4.0
4.0
6.0
6.0
Rev. 1.3 (Aug. 2001)
V/ns
Unit
V
V
V
V
V
Unit
uF
uF
Unit
pF
pF
pF
pF
pF
Note