AM49DL323BGT85S AMD [Advanced Micro Devices], AM49DL323BGT85S Datasheet
AM49DL323BGT85S
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AM49DL323BGT85S Summary of contents
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Am49DL32xBG Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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PRELIMINARY Am49DL32xBG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL32xG 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM with Page Mode DISTINCTIVE ...
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GENERAL DESCRIPTION Am29DL32xG Features The Am29DL322G/323G/324G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . ...
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Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59 Flash Data Retention . . . . . . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Standard Voltage Range: Options V = 2.7–3 Max Access Time, ns Page Access Time (pSRAM), ns CE#f Access, ns OE# Access, ns MCP BLOCK DIAGRAM A20 to A0 A20 to A0 A–1 ...
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FLASH MEMORY BLOCK DIAGRAM A20–A0 RY/BY# A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND CIOf REGISTER WP#/ACC DQ15–DQ0 A20– Upper Bank Address Upper Bank ...
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CONNECTION DIAGRAM LB UB A18 A17 DQ1 ...
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PIN DESCRIPTION A20– Address Inputs (Common) A Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (pSRAM) CE2s = Chip Enable 2 (pSRAM) OE# = Output ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49DL32x AMD DEVICE NUMBER/DESCRIPTION Am49DL32xBG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL32xG 32Megabit ( 8-Bit 16-Bit) CMOS 3.0 ...
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MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a ...
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Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s (Notes 1, 2) (Note 7) H Read from L Flash (Note 8) H (Note 7) H Write to Flash L (Note Standby H ...
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FLASH DEVICE BUS OPERATIONS Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 ...
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I f and the table represent the cur- CC6 CC7 rent specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to ...
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Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 ...
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Table 4. Top Boot Sector Addresses (Continued) Sector Address Sector SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Note: The address range is A20:A-1 in ...
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Sector Address Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 ...
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Table 6. Bottom Boot Sector Addresses (Continued) Sector Address Sector SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Note: The address range is A20:A-1 in ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip ...
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Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A20–A12 SA70 111111XXX 111110XXX, SA69-SA67 111101XXX, 111100XXX SA66-SA63 1110XXXXX SA62-SA59 1101XXXXX SA58-SA55 1100XXXXX SA54-SA51 1011XXXXX SA50-SA47 1010XXXXX SA46-SA43 1001XXXXX SA42-SA39 1000XXXXX SA38-SA35 0111XXXXX SA34-SA31 0110XXXXX SA30-SA27 0101XXXXX SA26-SA23 0100XXXXX SA22–SA19 ...
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Figure 1. Temporary Sector Unprotect Operation START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indica- tor Bit to ...
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CE#f and WE# must be a logical zero while OE logical one. Power-Up Write Inhibit If WE and OE the device does not accept commands on the rising edge of WE#. ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word Mode) (Byte Mode) 27h 4Eh 28h 50h ...
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Table 13. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Tables 15 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper ...
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The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. Tables 15 and 16 show the ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: Seefor program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for infor- mation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- ...
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Table 14. Command Definitions (Flash Word Mode) Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Manufacturer ID 4 555 Device ID 4 555 SecSi Sector Factory 4 555 Protect (Note 9) Sector Protect ...
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Table 16. Command Definitions (Flash Byte Mode) Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID 6 SecSi Sector Factory Protect 4 (Note 9) Sector Protect Verify 4 (Note 10) Enter SecSi ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsec- tions describe the function of these bits. DQ7 and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +125 C Ambient Temperature with Power Applied . . . . . . . . ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V Active Read Current CC1 ...
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DC & OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Operating Current CC1 Page Access Operating I s CC2 Current V Output Low Voltage OL V Output High Voltage ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6 Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 12. Input Waveforms ...
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AC CHARACTERISTICS CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR E#f E1#s E2s Figure 13. Timing Diagram for Alternating July 19, 2002 — t ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width ...
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FLASH AC CHARACTERISTICS Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching High to Output Active FHQV CE#f OE# ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS otes program address program data Illustration ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data RY/BY# t VCS otes: . SADD = sector address (for Sector Erase), ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH t DS Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect, ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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AC CHARACTERISTICS Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time CO t Output Enable Access Time OE t Data Byte Control Access Time BA t Chip Enable ...
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AC CHARACTERISTICS Addresses Addresses A3 to A20 CE#1 CE2 OE# WE# LB#, UB# D OUT I/ ACC Notes and t are defined as the time at ...
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AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Write Pulse Time WP t Chip Enable to End of Write CW t Data Byte Control to End of Write BW t Address Setup Time AS ...
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AC CHARACTERISTICS Addresses A0 to A20 t AS WE# CE CE2 LB#, UB# D High-Z OUT I/ (Note 1) I/ Notes the device is using the I/Os to output ...
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AC CHARACTERISTICS Addresses A0 to A20 t AS WE# CE CE2 UB#, LB# D High-Z OUT I/ (Note Notes the device is using the I/Os to output ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the ...
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DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t CE2 Setup Time CS t CE2 Hold Time CH t CE2 Pulse Width DPD t CE2 Hold from CE#1 CHC ...
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ADDRESS SKEW CE#1 WE# Address Note: If multiple invalid address cycles shorter than t cycle over t is required during that period. RC min CE#1 WE# Address Note: If multiple invalid address cycles shorter than t cycle over t ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array Am49DL32xBG July 19, 2002 ...
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REVISION SUMMARY Revision A (March 8, 2002) Initial release. Revision A+1 (July 19, 2002) Table 8. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection Added Table. Table 12. Command Definitions (Flash Word Mode) Table 13. Command Definitions (Flash Byte Mode) Modified ...