AM41LV3204MB10IT AMD [Advanced Micro Devices], AM41LV3204MB10IT Datasheet - Page 58

• Manufacturer Part Number: AM41LV3204MB10IT
• Description: Stacked Multi-chip Package (MCP) 32 Mbit (4 M x 8 bit/2 M x 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
June 10, 2003
Parameter
Address
CE1#s
CE2s
WE#
Data In
Data Out
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Symbol
t
t
is measured from the address valid to the beginning of write.
t
t
t
t
t
t
t
t
WHZ
t
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
WC
AW
BW
WP
WR
DW
OW
Cw
DH
AS
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Figure 28. SRAM Write Cycle—WE# Control
WP
Data Undefined
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 3)
P R E L I M I N A R Y
t
AS
Am41LV3204M
WR
t
WHZ
(See Note 1)
(See Note 1)
applied in case a write ends as CE1#s or WE# going high.
t
AW
(See Note 4)
t
WC
t
Max
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
CW
CW
t
WP
t
DW
WP
Data Valid
is measured from the beginning of write
Speed Option
10
70
60
60
60
50
20
30
t
0
0
0
0
5
DH
t
t
WR
OW
High-Z
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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