S71NS-N-MCP SPANSION [SPANSION], S71NS-N-MCP Datasheet - Page 5
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S71NS-N-MCP
Manufacturer Part Number
S71NS-N-MCP
Description
MirrorBit 1.8 Volt-only Simultaneous Read/Write, Burst-mode Multiplexed Flash Memory
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71NS-N-MCP.pdf
(12 pages)
2
October 10, 2006 S71NS-N_00_A3
Input/Output Descriptions
Table 2.1
AMAX – A16
ADQ15 – ADQ0
OE#
WE#
V
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
SS
Symbol
identifies the input and output package connections provided on the device.
A d v a n c e
Address inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the
pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent
active edges of CLK increment the internal address counter. Should be at
V
Address Valid input. Indicates to device that the valid address is present
on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode,
causes starting address to be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array
data
Hardware write protect input. At V
in the four outermost sectors. Should be at V
Accelerated input. At V
device in unlock bypass mode. At V
functions. Should be at V
Chip-enable input for pSRAM.
Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode.
Control Register Enable (pSRAM).
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
IL
or V
IH
while in asynchronous mode
I n f o r m a t i o n
Table 2.1 Input/Output Descriptions
S71NS-N MCP Products
HH
, accelerates programming; automatically places
IH
for all other conditions.
Description
IL
, disables program and erase functions
IL
, disables all program and erase
IH
for all other conditions.
Flash
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RAM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3