AT52BC6402A-85CI ATMEL [ATMEL Corporation], AT52BC6402A-85CI Datasheet - Page 31
AT52BC6402A-85CI
Manufacturer Part Number
AT52BC6402A-85CI
Description
64 MBIT FLASH 16 MBIT PSRAM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT52BC6402A-85CI.pdf
(38 pages)
- Current page: 31 of 38
- Download datasheet (347Kb)
Timing Diagrams
Power-up Sequence Timing
Note:
Deep Power-down Entry/Exit Sequence Timing
Note:
Standby Mode Characteristics Timing
Deep Power-down Mode Characteristics Timing
3441B–STKD–11/04
Power-up time is defined when CS2 is kept high before V
low level to high level, after V
When switching CS2 from high level to low level, the device will be in the deep power-down. In this case, an internal refresh
stops and the data might be lost.
V
CS1
CS2
CS1
ISB1
IDPD
CS2
CS1
CS2
CC
Suspend 1 µs
Suspend
1 µs
t
RC
CC
reached specified level, it is defined as the deep power-down exit.
Deep Power-down Mode
Wait 200 µs
Standby Mode
Deep Power-down Mode
CC
reaches specified minimum level. In case of CS2 is switched from
Wait 200 µs
Normal Operation
AT52BC6402A(T)
Normal Operation
31
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