HI-3585PCI HOLTIC [Holt Integrated Circuits], HI-3585PCI Datasheet

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HI-3585PCI

Manufacturer Part Number
HI-3585PCI
Description
ARINC 429 May 2009 Terminal IC with SPI Interface
Manufacturer
HOLTIC [Holt Integrated Circuits]
Datasheet
FEATURES
GENERAL DESCRIPTION
The HI-3585 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to the ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, 32 x 32 Receive FIFO and analog line receiver.
The independent transmitter has a 32 x 32 Transmit FIFO
and built-in line driver. The status of the transmit and
receive FIFOs can be monitored using the programmable
external interrupt pin, or by polling the HI-3585 Status
Register. Other features include a programmable option
of data or parity in the 32nd bit, and the ability to switch the
bit-signifiance of ARINC 429 labels. Pins are available
with different input resistance and output resistance
values which provides flexibility when using external
lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI.
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V or 5V operation.
The HI-3585 applies the ARINC 429 protocol to the
receiver and transmitter.
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
(DS3585 Rev. B)
May 2009
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ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
On-chip analog line driver and receiver connect
Programmable label recognition for 256 labels
32 x 32 Receive FIFO and 32 x 32 Transmit FIFO
Independent data rates for Transmit and Receive
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
directly to ARINC 429 bus
ARINC 429 databus timing
Alternatively, the SPI
HOLT INTEGRATED CIRCUITS
www.holtic.com
PIN CONFIGURATIONS
RINB-40 - 2
Terminal IC with SPI Interface
RINB - 3
N/C - 1
N/C - 4
N/C - 5
N/C - 6
N/C - 10
N/C - 11
MR - 7
CS
SI - 8
44 - Pin Plastic Quad Flat Pack (PQFP)
RINB-40 - 2
- 9
RINB - 3
N/C - 1
N/C - 4
N/C - 5
N/C - 6
N/C - 10
N/C - 11
MR - 7
CS
SI - 8
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
- 9
HI-3585PCT
HI-3585PCI
HI-3585PQT
HI-3585PQI
HI-3585
ARINC 429
(Top View)
33 - BOUT27
32 - BOUT37
31 - N/C
30 - V-
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
33 - BOUT27
32 - BOUT37
31 - N/C
30 - V-
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
05/09

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HI-3585PCI Summary of contents

Page 1

... RINB - Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com HI-3585 ARINC 429 (Top View BOUT27 32 - BOUT37 HI-3585PCI TFLAG HI-3585PCT RFLAG BOUT27 32 - BOUT37 N/C HI-3585PQI 28 - TFLAG HI-3585PQT RFLAG ...

Page 2

... SPI interface serial data input CS INPUT Chip select. Data is shifted into SI and out of SO when SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK GND POWER Chip 0V supply ACLK INPUT Master timing source for the ARINC 429 receiver and transmitter ...

Page 3

... Write the Control Register 11 None Reset the Transmit FIFO. 12 None Transmission enabled by this instruction only if Control Register bit 13 is zero HI-3585 Table 1 lists all instructions. Instructions that perform a reset or set, or enable transmission are executed after the last SI bit is received while CS is still low. ...

Page 4

... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3585 contains a 16-bit Control Register which is used to configure the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: ...

Page 5

... Null sampling ONE shift register and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift reg- ister. This guarantees the minimum pulse width. NULL 3. To validate the receive data bit rate, each bit must follow ...

Page 6

... Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. The adjacent table describes this operation. SCK CS SI ...

Page 7

... Receive FIFO ARINC words may be held in the Receive FIFO. Status register bit 2 (SR2) goes high when the Receive FIFO is full. Failure to unload the Receive FIFO when full causes additional received valid ARINC words to overwrite Receive FIFO location 32. ...

Page 8

... Once the Transmit FIFO is empty and transmission of the last word is complete, the FIFO can be loaded with new data which is held until the next SPI 12 hex instruction is executed. Once transmission is enabled, the FIFO positions are incremented with the top register loading into the data transmission shift register ...

Page 9

... TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance TXAOUT ARINC BIT TXBOUT DATA NULL BIT 30 BIT 31 ARINC DATA BIT 32 RFLAG t RFLG CS SPI INSTRUCTION 08h, (or 09h HI-3585 SERIAL INPUT TIMING DIAGRAM t CYC t t CES CES t t SCKR ...

Page 10

... BOUT) 10% one level HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3585PCI and HI-3585PCT use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the ABSOLUTE MAXIMUM RATINGS Supply Voltages V ...

Page 11

... Input Sink I IH Input Source I IL Differential C (RINA to RINB GND Input Voltage Input Sink I IH Input Source One or zero V No load and magnitude at pin, DOUT Null V NOUT One or zero ...

Page 12

... SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to RFLAG(Full or Empty Speed Delay - Last bit of received ARINC word to RFLAG(Full or Empty Speed Received data available to SPI interface. RFLAG to SPI receiver read or clear FIFO instruction to RFLAG ...

Page 13

... REVISION HISTORY Revision Date Description of Change DS3585,Rev. NEW 05/08/08 Initial Release Rev. A 10/10/08 Revised AC Electrical Characteristics table and description of “T” process. Rev. B 05/22/09 Clarified relationship between SPI bit order and the ARINC 429 bit order. HI-3585 HOLT INTEGRATED CIRCUITS 13 ...

Page 14

... PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A ...

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