HI-3282CDI-10 HOLTIC [Holt Integrated Circuits], HI-3282CDI-10 Datasheet - Page 4

• Manufacturer Part Number: HI-3282CDI-10
• Description: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each
receiver.
The ARINC 429 specification contains the following timing
specification for the received data:
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1",
data flag for a receiver will remain low until after
from that receiver are retrieved.
activating
byte and activating
BIT TIMING
PULSE FALL TIME
PULSE RISE TIME
PULSE WIDTH
BIT RATE
DECODER
CONTROL
EN
BITS
with SEL, the byte selector, low to retrieve the first
SEL
D/R
EN
ZEROS
ONES
EN
NULL
/
with SEL high to retrieve the second byte.
100K BPS ± 1% 12K -14.5K BPS
CONTROL
CONTROL
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
ENABLE
HIGH SPEED
LATCH
5 µsec ± 5%
MUX
D/R1
EOS
or
BITS 9 & 10
D/R2
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
This is accomplished by
(or both) will go low. The
34.5 to 41.7 µsec
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
FIGURE 2.
32 BIT SHIFT REGISTER
both
32 TO 16 DRIVER
HOLT INTEGRATED CIRCUITS
32 BIT LATCH
ARINC bytes
TO PINS
RECEIVER BLOCK DIAGRAM
HI-3282
4
EN1
receiver 2.
If another ARINC word is received and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
INTERNAL LIGHTNING PROTECTION (-10 Only)
The HI-3282-10 configurations are similar to the HI-3282 except
that the ARINC inputs are internally lightning protected to
DO-160D, Level 3 through 10 Kohm resistors that
connected in series with each input from the ARINC bus.
The design of the HI-3282-10 device requires the external
10 Kohm series resistors for proper ARINC level detection. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10 Kohm resistors, they are just below the
standard 6.5 V minimum ARINC data threshold and just above the
2.5 V maximum ARINC null threshold.
The receivers of the HI-3282-10 when used with external 10
Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4
and 5A. No additional lightning protection circuit is necessary.
APPLICATION NOTE 300
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
WORD GAP
BIT CLOCK
DATA
retrieves data from receiver 1 and
START
CONTROL
BIT BD14
PARITY
CHECK
WORD GAP
SEQUENCE
DETECTION
CONTROL
ERROR
TIMER
32ND
BIT
EOS
END
ERROR
CLOCK
SEQUENCE
COUNTER
BIT CLOCK
END OF
OPTION
CLOCK
AND
BIT
EN2
CLOCK
retrieves data from
CLK
must
be