AFE8201PFBR BURR-BROWN [Burr-Brown Corporation], AFE8201PFBR Datasheet - Page 10

• Manufacturer Part Number: AFE8201PFBR
• Description: IF Analog-to-Digital Converter with Digital Downconverter
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

AFE8201
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
DATA INTERFACE
The data interface consists of six signals:
The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data
outputs. The control DAC data is shifted into the data input. Control Register 0 programs the functionality of the data
interface, as seen in Figure 11.
Two parameters, DIV and MODE, control the data interface and are programmed by register 0. The first parameter
is DIV. The serial data clock, DCLKO, is derived from MCLK in a manner controlled by DIV such that the frequency
of DCLKO is:
where DIV ranges from 0 to 3.
As an example, if MCLK is 80MHz, DCLK0 can be either 80MHz, 40MHz, 20MHz, or 10MHz. DCLK0, of course, must
be fast enough to clock out the I and Q data words generated by the on-chip DDC and filters.
The second parameter is MODE. When MODE is 0, all four DDC outputs are time multiplexed onto DOUT0, as shown
in Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are
multiplexed onto DOUT1, see Figure 13. If only one set of I/Q outputs is used, MODE 1 is recommended so that data
is output through DOUT0.
10
DCLKO
DOUT0
DOUT1
1. serial data clock DCLKO;
2. output frame sync DFSO;
3. output data line DOUT0;
4. output data line DOUT1;
5. input frame sync DFSI; and
6. input data line DIN.
DFSO
DFSI
0
DIN
Register Address
0
0
MSB
0
0
15
IA
14
Figure 12. Data Interface Timing for MODE = 0
13
Figure 11. Data Interface Control Register
LSB
12
11
QA
MSB
f
DCLKO
10
+
Don’t Care
f
9
2
MCLK
DAC
DIV
8
7
LSB
IB
6
5
4
3
QB
2
DIV
1
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MODE
0
(1)