MBM29LV800B-12PFTN Fujitsu, MBM29LV800B-12PFTN Datasheet
MBM29LV800B-12PFTN
Manufacturer Part Number
MBM29LV800B-12PFTN
Description
Manufacturer
Fujitsu
Datasheet
1.MBM29LV800B-12PFTN.pdf
(50 pages)
Specifications of MBM29LV800B-12PFTN
Case
TSOP
Date_code
97+
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Company:
Part Number:
MBM29LV800B-12PFTN
Manufacturer:
FUJITSU
Quantity:
1 254
FUJITSU SEMICONDUCTOR
FLASH MEMORY
CMOS
8M (1M
MBM29LV800T/MBM29LV800B
Embedded Erase
DISTINCTIVE CHARACTERISTICS
• Single 3.0 V read, write, and erase
• Compatible with JEDEC-standard commands
• Compatible with JEDEC-standard word-wide pinouts
• Minimum 100,000 write/erase cycles
• High performance
• Sector erase architecture
• Boot Code Sector Architecture
• Embedded Erase
• Embedded Program
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
• Low power consumption
• Low V
• Erase Suspend/Resume
DATA SHEET
Minimizes system level power requirements
Uses same software commands as E
48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
120 ns maximum access time
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
T = Top sector
B = Bottom sector
Automatically pre-programs and erases the chip or any sector
Automatically writes and verifies data at specified address
Hardware method for detection of program or erase cycle completion
40 mA maximum active read current for Byte Mode
45 mA maximum active read current for Word Mode
50 mA maximum write/erase current
250 A typical standby current
Suspends the erase operation to allow a read in another sector within the same device
CC
TM
write inhibit
and Embedded Program
TM
Algorithms
TM
Algorithms
2.3 V
TM
8/512K
are trademarks of Advanced Micro Devices, Inc.
2
PROMs
16)
DS05-20819-1E
(Continued)
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