AGLE3000V2-FGG896I Actel, AGLE3000V2-FGG896I Datasheet

AGLE3000V2-FGG896I

Manufacturer Part Number

AGLE3000V2-FGG896I

Description

PBGA 896/FPGA, 75264 CLBS, 3000000 GATES, 250 MHz

Manufacturer

Actel

Datasheet

1.AGLE3000V2-FGG896I.pdf (156 pages)

Specifications of AGLE3000V2-FGG896I

Lead_time

Pack_quantity

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

AGLE3000V2-FGG896I

Manufacturer:

Microsemi SoC

Quantity:

10 000

Current page: 1 of 156
Download datasheet (4Mb)

October 2008

IGLOOe Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

High Capacity

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

IGLOOe Product Family

IGLOOe Devices

ARM-Enabled IGLOOe Devices

System Gates

VersaTiles (D-flip-flops)

Quiescent Current (typical) in Flash*Freeze Mode (µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. Refer to the

2. Six chip (main) and twelve quadrant global networks are available.

3. For devices supporting lower densities, refer to the

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze

• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

FBGA

Consumption while Maintaining FPGA Content

Power Flash*Freeze Mode

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

Cortex-M1 Handbook

Technology

Enables

for more information.

Ultra-Low

IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology

Power

Pro (Professional) I/O

Clock Conditioning Circuit (CCC) and PLL

Embedded Memory

ARM Processor Support in IGLOOe FPGAs

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.2

• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

• I/O Registers on Input, Output, and Enable Paths

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO

• Six CCC Blocks, Each with an Integrated PLL

• Configurable

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• True Dual-Port SRAM (except ×18)

• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

M-LVDS

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

Capabilities, and External Feedback

Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

with or without Debug

FG256, FG484

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

AGLE600

13,824

600 k

108

270

Yes

1 k

I/O

Phase

Standards:

Shift,

LVTTL,

Multiply/Divide,

FG484, FG896

M1AGLE3000

AGLE3000

75,264

3 M

137

504

112

620

Yes

1 k

LVCMOS

e Family

handbook.

v1.2

3.3 V /

Delay

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