AFS1500-2FGG256I Actel, AFS1500-2FGG256I Datasheet

AFS1500-2FGG256I

Manufacturer Part Number

AFS1500-2FGG256I

Description

Manufacturer

Actel

Datasheet

1.AFS1500-2FG256I.pdf (318 pages)

Specifications of AFS1500-2FGG256I

Lead_time

Pack_quantity

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

AFS1500-2FGG256I

Manufacturer:

Microsemi SoC

Quantity:

10 000

Current page: 1 of 318
Download datasheet (8Mb)

October 2008

Actel Fusion Mixed-Signal FPGAs

Family with Optional ARM

Features and Benefits

High-Performance Reprogrammable Flash

Technology

Embedded Flash Memory

Integrated A/D Converter (ADC) and Analog I/O

On-Chip Clocking Support

Fusion Family

Fusion Devices

ARM-Enabled

Fusion Devices

General

Information

Memory

Analog and I/Os

Notes:

1. Refer to the

2. Refer to the

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Nonvolatile, Retains Program when Powered Off

• Live at Power-Up (LAPU) Single-Chip Solution

• 350 MHz System Performance

• User Flash Memory – 2 Mbits to 8 Mbits

• 1 kbit of Additional FlashROM

• Up to 12-Bit Resolution and up to 600 ksps

• Internal 2.56 V or External Reference Voltage

• ADC: Up to 30 Scalable Analog Input Channels

• High-Voltage Input Tolerance: –10.5 V to +12 V

• Current Monitor and Temperature Monitor Blocks

• Up to 10 MOSFET Gate Driver Outputs

• ADC Accuracy is Better than 1%

• Internal 100 MHz RC Oscillator (accurate to 1%)

• Crystal Oscillator Support (32 kHz to 20 MHz)

• Programmable Real-Time Counter (RTC)

• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths

PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

CoreMP7

Cortex-M1

CoreMP7

Cortex-M1

System Gates

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

datasheet for more information.

product brief for more information.

Support

AFS090

90,000

2,304

2 M

Yes

1 k

Low Power Consumption

In-System Programming (ISP) and Security

Advanced Digital I/O

SRAMs and FIFOs

Soft ARM7™ Core Support in M7 and M1 Fusion Devices

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low Power Modes

• Secure ISP with 128-Bit AES via JTAG

• FlashLock

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and Weak

• Pin-Compatible Packages across the Fusion Family

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

• ARM Cortex™-M1 (without debug), CoreMP7Sd (with

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

3.3 V / 2.5 V /1.8 V / 1.5 V,

LVCMOS 2.5 V / 5.0 V Input

– Built-In I/O Registers

– 700 Mbps DDR Operation

Pull-Up/Down Resistor

and ×18 organizations available)

debug) and CoreMP7S (without debug)

M1AFS250

250,000

AFS250

6,144

2 M

114

Yes

1 k

to Secure FPGA Contents

I/O

Standards:

M7AFS600

M1AFS600

600,000

AFS600

3.3 V PCI

13,824

4 M

108

172

Yes

1 k

Preliminary v1.7

LVTTL,

3.3 V PCI-X,

M1AFS1500

1,500,000

AFS1500

38,400

8 M

270

252

Yes

1 k

LVCMOS

and

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