A54SX16-PQ208 Actel, A54SX16-PQ208 Datasheet

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A54SX16-PQ208

Manufacturer Part Number
A54SX16-PQ208
Description
Manufacturer
Actel
Datasheet

Specifications of A54SX16-PQ208

Lead_time
7
Pack_quantity
24
Analog
ACLA54SX16PQG208
Comm_code
85423990

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54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
• 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• 0.35µ CMOS
S X P r od u c t P ro fi l e
J u n e 2 0 0 3
© 2003 Actel Corporation
Capacity
Logic Modules
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
Typical Gates
System Gates
Combinatorial Cells
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
Std, –1, –2, –3
A54SX08
144, 176
12,000
C, I, M
3.7 ns
0.8 ns
8,000
768
512
256
130
Yes
208
100
144
84
3
F ea t u r es
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with
• Boundary Scan Testing in Compliance with IEEE Standard
• Secure Programming Technology Prevents Reverse
Std, –1, –2, –3
A54SX16
Silicon Explorer II
1149.1 (JTAG)
Engineering and Design Theft
16,000
24,000
C, I, M
3.9 ns
0.5 ns
1,452
924
528
175
Yes
208
100
176
3
Std, –1, –2, –3
A54SX16P
144, 176
16,000
24,000
C, I, M
4.4 ns
0.5 ns
1,452
924
528
175
Yes
Yes
208
100
3
Std, –1, –2, –3
A54SX32
144, 176
313, 329
32,000
48,000
C, I, M
4.6 ns
0.1 ns
2,880
1,080
1800
249
208
Yes
3
v 3 . 1
1

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