A3PE3000-1FGG896I Actel, A3PE3000-1FGG896I Datasheet
A3PE3000-1FGG896I
Manufacturer Part Number
A3PE3000-1FGG896I
Description
BGA 896/IC,FPGA,75264-CELL,CMOS
Manufacturer
Actel
Datasheet
1.A3PE3000-1FGG896I.pdf
(152 pages)
Specifications of A3PE3000-1FGG896I
Lead_time
280
Pack_quantity
27
Comm_code
85423990
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PE3000-1FGG896I
Manufacturer:
Microsemi SoC
Quantity:
10 000
March 2008
© 2008 Actel Corporation
ProASIC3E Flash Family FPGAs
with Optional Soft ARM
Features and Benefits
High Capacity
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory
High Performance
In-System Programming (ISP) and Security
Low Power
High-Performance Routing Hierarchy
Pro (Professional) I/O
Table 1-1 • ProASIC3E Product Family
ProASIC3E Devices
Cortex-M1 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. Refer to the
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 1 kbit of FlashROM with Synchronous Interfacing
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
• 700 Mbps DDR, LVDS-Capable I/Os
PQFP
FBGA
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
®
to Secure FPGA Contents
Cortex-M1
3
1
2
product brief for more information.
®
Support
FG256, FG484
A3PE600
13,824
PQ208
600 k
108
270
Yes
1 k
24
18
6
8
ProASIC3 Flash Family FPGAs
Clock Conditioning Circuit (CCC) and PLL
SRAMs and FIFOs
ARM
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
• Six CCC Blocks, Each with an Integrated PLL
• Configurable
• Wide Input Frequency Range (1.5 MHz to 200 MHz)
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
M-LVDS
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
Capabilities and External Feedback
and ×18 organizations available)
Operation up to 350 MHz
with or without Debug
®
Processor Support in ProASIC3E FPGAs
FG484, FG676
M1A3PE1500
A3PE1500
38,400
PQ208
1.5 M
270
444
Yes
1 k
60
18
6
8
handbook.
I/O
Phase-Shift,
Standards:
FG324
Multiply/Divide,
LVTTL,
M1A3PE3000
A3PE3000
,
75,264
PQ208
FG484, FG896
3 M
504
112
620
Yes
1 k
LVCMOS
18
6
8
®
3E Family
v1.0
3.3 V /
Delay
®
I
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