A1020B-2 Actel, A1020B-2 Datasheet

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A1020B-2

Manufacturer Part Number
A1020B-2
Description
Manufacturer
Actel
Datasheet

Specifications of A1020B-2

Case
QFP/100
Date_code
97+

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ACT
F e a t u re s
• 5V and 3.3V Families fully compatible with JEDEC
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
D e s c r ip t i on
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
The user-definable I/Os are capable of driving at both TTL
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
Apr i l 199 6
© 1996 Actel Corporation
specifications
Place and Route
Analysis to 25 MHz
®
antifuse technology. The unique architecture offers
1 Series FPGAs
®
Packages
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Pr o d u c t F a m i ly P r o fi l e
Th e D e s i g n e r a n d D e s ig n e r
A d v a n t a g e ™ Sy s t e ms
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap
and the ACTgen
generator for counters, adders, and other structural blocks.
Device
Capacity
Logic Modules
Flip-Flops (maximum)
Routing Resources
User I/Os (maximum)
Packages:
Performance
Note:
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
See Product Plan on page 1-286 for package availability.
®
Windows
Macro Builder, a powerful macro function
VHDL optimization and synthesis tool
and X Windows
100 PQFP
A10V10B
84 CPGA
44 PLCC
68 PLCC
80 VQFP
A1010B
112,000
75 MHz
55 MHz
1,200
3,000
295
147
30
12
22
13
57
graphical user
100 PQFP
A10V20B
84 CPGA
84 CQFP
44 PLCC
68 PLCC
84 PLCC
80 VQFP
A1020B
186,000
75 MHz
55 MHz
2,000
6,000
1-283
547
273
50
20
22
13
69

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