74VHC00 Fairchild Semiconductor, 74VHC00 Datasheet

74VHC00

Manufacturer Part Number

74VHC00

Description

Manufacturer

Fairchild Semiconductor

Datasheets

1.74VHC00.pdf (7 pages)

2.74VHC00.pdf (7 pages)

Specifications of 74VHC00

Case

SOP-14

Date_code

98-99+/SZ

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Download datasheet (102Kb)

74VHC00M

74VHC00MX_NL

74VHC00SJ

74VHC00MTC

74VHC00MTCX_NL

(Note 1)

74VHC00N

74VHC00

Quad 2-Input NAND Gate

General Description

The VHC00 is an advanced high-speed CMOS 2-Input

NAND Gate fabricated with silicon gate CMOS technology.

It achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The internal circuit is composed of 3

stages, including buffer output, which provide high noise

immunity and stable output. An input protection circuit

insures that 0V to 7V can be applied to the input pins with-

out regard to the supply voltage. This device can be used

to interface 5V to 3V systems and two supply systems such

as battery backup. This circuit prevents device destruction

due to mismatched supply and input voltages.

Ordering Code:

Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol

Pin Descriptions

Order Number

, B

Pin Names

Package

Number

MTC14

M14A

M14D

N14A

IEEE/IEC

Inputs

Outputs

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Description

DS011504

Features

Connection Diagram

Truth Table

High Speed: t

High noise immunity: V

Power down protection is provided on all inputs

Low noise: V

Low power dissipation: I

Pin and function compatible with 74HC00

Package Description

OLP

3.7ns (typ) at T

0.8V (max)

NIH

October 1992

Revised February 2005

2 A (max) at T

NIL

28% V

www.fairchildsemi.com

25 C

(min)

25 C

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