74LVQ151SJ Fairchild Semiconductor, 74LVQ151SJ Datasheet - Page 2

• Manufacturer Part Number: 74LVQ151SJ
• Description: MULTIPLEXER LV 8INPUT 16SOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LVQr
• Type: Multiplexerr

Specifications of 74LVQ151SJ

• Circuit: 1 x 8:1
• Independent Circuits: 1
• Current - Output High, Low: 12mA, 12mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Logical Function: Mux
• Configuration: 1 x 8:1
• Number Of Inputs: 8
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOP W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Truth Table
H
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
X
LOW Voltage Level
HIGH Voltage Level
Immaterial
E
H
L
L
L
L
L
L
L
L
S
X
H
H
H
H
L
L
L
L
2
Inputs
S
H
H
H
H
X
L
L
L
L
1
S
X
H
H
H
H
L
L
L
L
0
H
I
I
I
I
I
I
I
I
Z
0
1
2
3
4
5
6
7
Outputs
I
I
I
I
I
I
I
I
Z
L
0
1
2
3
4
5
6
7
2
Functional Description
The LVQ151 is a logic implementation of a single pole, 8-
position switch with the switch position controlled by the
state of three Select inputs, S
plementary outputs are provided. The Enable input (E) is
active LOW. When it is not activated, the complementary
output is HIGH and the true output is LOW regardless of all
other inputs. The logic function provided at the output is:
Z
The LVQ151 provides the ability, in one package to select
from eight sources of data or control information. By proper
manipulation of the inputs, the LVQ151 can provide any
logic function of four variables and its complement.
I
I
I
E • (I
2
4
6
• S
• S
• S
0
0
0
0
• S
• S
• S
• S
0
1
1
1
• S
• S
• S
• S
2
1
2
2
• S
I
I
I
7
3
5
2
• S
• S
• S
0
I
0
0
1
• S
0
• S
• S
• S
, S
1
1
0
1
1
• S
• S
, S
• S
• S
2
2
2
)
. Both true and com-
1
2
• S
2