74LVX138M Fairchild Semiconductor, 74LVX138M Datasheet - Page 2

• Manufacturer Part Number: 74LVX138M
• Description: DECODER/DEMUX 1-OF-8 LV 16SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74LVXr
• Type: Decoder/Demultiplexerr

Specifications of 74LVX138M

• Circuit: 1 x 3:8
• Independent Circuits: 1
• Current - Output High, Low: 4mA, 4mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: 74LV
• Number Of Lines (input / Output): 1.0 / 8.0
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 1.0
• Number Of Output Lines: 8.0
• Power Dissipation: 180 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
The LVX138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A
when enabled, provides eight mutually exclusive active-
LOW outputs (O
inputs, two active-LOW (E
Truth Table
H
L
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
LOW Voltage Level
HIGH Voltage Level
Immaterial
E
H
X
X
L
L
L
L
L
L
L
L
1
0
–O
7
). The LVX138 features three Enable
E
H
X
X
L
L
L
L
L
L
L
L
2
1
, E
E
X
X
H
H
H
H
H
H
H
H
L
2
Inputs
3
) and one active-HIGH (E
A
X
X
X
H
H
H
H
L
L
L
L
0
0
A
H
H
H
H
, A
X
X
X
L
L
L
L
1
1
, A
A
X
X
X
H
H
H
H
L
L
L
L
2
2
) and,
3
O
).
H
H
H
H
H
H
H
H
H
H
L
0
2
All outputs will be HIGH unless E
is HIGH.
The LVX138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data
input and the other Enable inputs as strobes. The Enable
inputs which are not used must be permanently tied to their
appropriate active-HIGH or active-LOW state.
O
H
H
H
H
H
H
H
H
H
H
L
1
O
H
H
H
H
H
H
H
H
H
H
L
2
O
Outputs
H
H
H
H
H
H
H
H
H
H
L
3
O
H
H
H
H
H
H
H
H
H
H
L
4
O
H
H
H
H
H
H
H
H
H
H
L
5
1
and E
O
H
H
H
H
H
H
H
H
H
H
L
6
2
are LOW and E
O
H
H
H
H
H
H
H
H
H
H
L
7
3