ADSP21160NCBZ100 Analog Devices, ADSP21160NCBZ100 Datasheet

ADSP21160NCBZ100

Manufacturer Part Number

ADSP21160NCBZ100

Description

BGA400

Manufacturer

Analog Devices

Datasheet

1.ADSP21160NCBZ100.pdf (60 pages)

Specifications of ADSP21160NCBZ100

Date_code

09+

Current page: 1 of 60
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SUMMARY

High performance 32-bit DSP—applications in audio, medi-

Super Harvard architecture—4 independent buses for dual

Backward compatible—assembly source level compatible

Single-instruction, multiple-data (SIMD) computational

Integrated peripherals—integrated I/O processor, 4M bits

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

cal, military, graphics, imaging, and communication

data fetch, instruction fetch, and nonintrusive, zero-over-

head I/O

with code for ADSP-2106x DSPs

architecture—two 32-bit IEEE floating-point computation

units, each with a multiplier, ALU, shifter, and register file

on-chip dual-ported SRAM, glueless multiprocessing fea-

tures, and ports (serial, link, external bus, and JTAG)

8 x 4 x 32

DAG1

CONNECT

MULT

BUS

(PX)

8 x 4 x 32

16 x 40-BIT

DAG2

DATA

(PEX)

CORE PROCESSOR

FILE

DM ADDRESS BUS

PM ADDRESS BUS

PM DATA BUS

DM DATA BUS

TIMER

BARREL

SHIFTER

ALU

SEQUENCER

PROGRAM

INSTRUCTION

32 x 48-BIT

CACHE

16/32/40/48/64

32/40/64

Figure 1. Functional Block Diagram

SHIFTER

BARREL

ALU

ADDR

PROCESSOR PORT

16 x 40-BIT

ADDR

(PEY)

DATA

FILE

DUAL-PORTED BLOCKS

TWO INDEPENDENT

DATA

DUAL-PORTED SRAM

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

FEATURES

100 MHz (10 ns) core instruction rate (ADSP-21160N)

Single-cycle instruction execution, including SIMD opera-

Dual data address generators (DAGs) with modulo and bit-

Zero-overhead looping and single-cycle loop setup, provid-

IEEE 1149.1 JTAG standard Test Access Port and on-chip

400-ball 27 mm × 27 mm PBGA package

Available in lead-free (RoHS compliant) package

200 million fixed-point MACs sustained performance

MULT

DATA

tions in both computational units

reverse addressing

ing efficient program sequencing

emulation

(ADSP-21160N)

ADSP-21160M/ADSP-21160N

DATA

I/O PORT

IOD

Digital Signal Processor

DATA BUFFERS

ADDR

STATUS AND

REGISTERS

CONTROL,

(MEMORY

MAPPED)

ADDR

IOP

IOA

I/O PROCESSOR

MULTIPROCESSOR

SERIAL PORTS

CONTROLLER

LINK PORTS

HOST PORT

INTERFACE

ADDR BUS

DATA BUS

EXTERNAL

DMA

(6)

(2)

MUX

PORT

EMULATION

TEST AND

JTAG

www.analog.com

SHARC

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