V3021SO8A EMMICRO [EM Microelectronic - MARIN SA], V3021SO8A Datasheet - Page 9

• Manufacturer Part Number: V3021SO8A
• Description: Ultra Low Power 1-Bit 32 kHz RTC
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

Pin Description
Functional Description
Serial Communication
The V3021 resides on the parallel data and address
buses as a standard peripheral (see Fig.13 and 14).
Address decoding provides an active low chip select
( CS ) to the device. For Intel compatible bus timing the
control signals RD and WR pulse and CS are used for
a single bit read or write (see Fig. 7a and 7b).
options exist for Motorola compatible bus timing. The first
is to use the control signals DS with R/ W and CS , the
second is to tie the RD input to CS and use the control
signals R/ W and CS (see Fig. 7a and 7c). Data transfer
is accomplished through a single input/output line (I/O).
Any data bus line can be chosen. A conventional 3 wire
serial interface can also be used to communicate with the
V3021 (see Fig. 15).
Communication Cycles
The V3021 has 3 serial communication cycles. These
are:
A communication cycle always begins by writing the 4
address bits, A0 to A3. A microprocessor read from the
V3021 cannot begin a communication cycle. Read and
write data cycles are similar and consist of 4 address bits
and 8 data bits. The 4 address bits, A0 to A3, define the
RAM location and the 8 data bits D0 and D7 provide the
relevant information. An address command cycle consists
of only 4 address bits.
Read Data Cycle
A read data cycle commences by writing the 4 RAM
address bits (A3, A2, A1 and A0) to the V3021. The LSB,
A0, is transmitted first (see Fig. 6a and 6b).
microprocessor reads from the V3021 will read the RAM
data at this address, beginning with the LSB, D0. The
read data cycle finishes on reading the 8
Write Data Cycle
A write data cycle commences by writing the 4 RAM
address bits (A3, A2, A1 and A0) to the V3021. The LSB,
A0, is transmitted first (see Fig. 8c and 8d).
microprocessor writes to the V3021 will write the new
RAM data. The LSB, D0, is loaded first. The write data
cycle finishes on writing the 8
Copyright © 2005, EM Microelectronic-Marin SA
Pin
1
2
3
4
5
6
7
8
1) Read data cycle
2) Write data cycle
3) Address command cycle
Name
WR
V
V
RD
XO
CS
I/O
XI
SS
DD
R
Function
32 kHz crystal input
32 kHz crystal output
Chip select input
Ground supply
Data input and output
Intel RD , Motorola DS (or tie to CS )
Intel WR , Motorola R/ W
Positive supply
th
data bit, D7.
th
data bit, D7.
Table 5
Eight
Eight
Two
Address Command Cycle
An address command cycle consists of just 4 address
bits. The LSB, A0, is transmitted first (see Fig. 8e and 8f).
On writing the fourth address bit, A3, the address will be
decoded. If the address bits are recognized as one of the
command codes E hex or F hex (see Table 6), then the
communication cycle is terminated and the corresponding
command is executed.
writes to the V3021 begin another communication cycle
with the first bit being interpreted as the address LSB, A0.
Clock Configuration
The V3021 has a reserved clock area and a user RAM
area (see Fig. 7). The clock is not directly accessible, it is
used for internal time keeping and contains the current
time and data. The contents of the RAM is shown in
Table 6, it contains a data space and an address
command space. The data space is directly accessible.
Addresses 0 and 1 contain status information (see Tables
7a and 7b), addresses 2 to 5, time data, and addresses 6
to 9, date data. The address command space is used to
issue commands to the V3021.
RAM Map
Commands
Two commands are available (see Table 6).
Copy_RAM_to_clock command is used to set the current
time and date in the clock and the Copy_clock_to_RAM
command to copy the current time and date from the clock
to the RAM.
address data E hex, causes the clock time and date to be
overwritten by the time and date stored in the RAM at
addresses 2 to 9. Address 1 is also cleared (see section
"Time and Date Status Bits").
command, the desired time and date must be loaded into
the RAM using write data cycles and the time set lock bit,
address 0, bit 4, must be clear (see section "Time Set
Lock").
9
Dec
Data Space
Address Command Space
14
15
0
1
2
3
4
5
6
7
8
9
Address
Hex
E
F
0
1
2
3
4
5
6
7
8
9
The Copy_RAM_to_clock command,
Parameter
Status 0
Status 1
Seconds
Minutes
Hours
Day of month
Month
Year
Week day
Week number
Copy_RAM_to_clock
Copy_clock_to_RAM
Subsequent microprocessor
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Prior to using this
V3021
range
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-52
BCD
Table 6
The