SX1231 SEMTECH [Semtech Corporation], SX1231 Datasheet - Page 68

• Manufacturer Part Number: SX1231
• Description: Low Power Integrated UHF Transceiver
• Manufacturer: SEMTECH [Semtech Corporation]

Rev 2 - Nov 2009
RegIrqFlags2
(0x28)
RegRssiThresh
(0x29)
RegRxTimeout1
(0x2A)
RegRxTimeout2
(0x2B)
ADVANCED COMMUNICATIONS & SENSING
7-0
7-0
7-0
7
6
5
4
3
2
1
0
FifoFull
FifoNotEmpty
FifoLevel
FifoOverrun
PacketSent
PayloadReady
CrcOk
LowBat
RssiThreshold
TimeoutRxStart
TimeoutRssiThresh
rwc
rwc
rw
rw
rw
r
r
r
r
r
r
Page 68
0xE4
0x00
0x00
0
0
0
0
0
0
0
*
-
Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
Set when FIFO contains at least one byte, else cleared
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold , else cleared.
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
transmission / reception.
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx.
Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared , is Ok). Cleared when FIFO is empty.
Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set by the user.
RSSI trigger level for Rssi interrupt :
Timeout interrupt is generated TimeoutRxStart *16*T
after switching to Rx mode if Rssi interrupt doesn’t occur
(i.e. RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
Timeout interrupt is generated TimeoutRssiThresh *16*T
after Rssi interrupt if PayloadReady interrupt doesn’t
occur.
0x00: TimeoutRssiThresh is disabled
- RssiThreshold / 2 [dBm]
DATASHEET
www.semtech.com
SX1231
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