PLRXPL-VE-SG4-62-X JDSU [JDS Uniphase Corporation], PLRXPL-VE-SG4-62-X Datasheet - Page 5

• Manufacturer Part Number: PLRXPL-VE-SG4-62-X
• Description: RoHS-Compliant 4.25 Gbps 850 nm eSFP Transceivers
• Manufacturer: JDSU [JDS Uniphase Corporation]

Notes
* Transmission lines should be 100 Ω differential traces. It is recommended that the termination resistor for the PECL Receiver (R3 + R4) be placed beyond the input pins of the
PECL Receiver. Series Source Termination Resistors on the PECL Driver (R1+R2) should be placed as close to the driver output pins as possible
5
Open Collector Driver
Receiver (Tx Fault)
Power supply fi ltering components should be placed as close to the V
(Mod_Def(0))
Receiver (LOS)
Open Collector
Open Collector
PECL driver and receiver will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported.
Rate Select
(Tx Disable)
(Mod_Def(2))
(Mod_Def(1))
Bidirectional
Bidirectional
Receiver
MOD_DEF(2) and MOD_DEF(1) should be bi-directional open collector connections in order to implement serial ID (MOD_DEF[0,1,1]) PLRXPL-VE-S64-62-x transceiver.
R1 and R2 may be included in the output of the PHY. Check application notes of the IC in use.
Figure 2
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Vcc
Vcc
Vcc
Vcc
Vcc
Recommended application schematic for the PLRXPL-VE-SG4-62-x transceiver
10 VeeR
1 VeeT
2 Tx Fault
3 Tx Disable
7 Rate Select
4 MOD_DEF(2)
5 MOD_DEF(1)
6 MOD_DEF(0)
8 LOS
9 VeeR
Section 2
Recommended connections to the PLRXPL-VE-SG4-62-x transceiver are shown
in Figure 2 below.
ROHS-COMPLIANT 4.25 GBPS 850 NM TRANSCEIVERS
cc
pins of the host connector as possible for optimal performance.
VeeT 20
VeeT 17
VccT 16
VccR 15
VeeR 14
RD+ 13
VeeR 11
TD- 19
TD+ 18
RD- 12
Application Schematics
0.1μF
0.1 μF
C3
C4
Z
*
= 100Ω
Z
*
= 100Ω
10 μF
C5
1 μH
1 μH
L1
L2
R1
R2
*
*
50Ω
50Ω
50Ω
50Ω
R3
R4
*
*
0.1 μF
C2
PECL Receiver
(RX DATA)
PECL Driver
(TX DATA)
Vcc +3.3V Input
10μF
C1