AT86RF230_09 ATMEL [ATMEL Corporation], AT86RF230_09 Datasheet - Page 15
AT86RF230_09
Manufacturer Part Number
AT86RF230_09
Description
Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT86RF230_09.pdf
(98 pages)
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Figure 6-11. Packet Structure - SRAM Write Access
Figure 6-12. Packet Structure - SRAM Read Access
Figure 6-13. Example SPI Sequence – SRAM Write Access Sequence of a 5 byte Data Package
SCLK
MOSI
MISO
5131E-MCU Wireless-02/09
SEL
COMMAND
XX
ADDRESS
The SRAM access mode is useful, for instance, if a transmit frame is already stored in
the Frame Buffer and certain bytes (e.g. sequence number or address field) need to be
replaced before retransmitting the frame. Furthermore, it can be used to access only
the LQI value after frame reception. A detailed description of the user accessible frame
content can be found in section 9.3.2.
Each access starts by setting SEL = L. The first transferred byte on MOSI shall be the
command byte and must indicate a SRAM access mode according to the definition in
Table 6-2. The following byte indicates the start address of the write or read access.
The address space is 0x00 to 0x7F. The microcontroller software has to ensure to
access only to the valid address space.
On SRAM write access, one or more bytes of write data are transferred on MOSI
starting with the third byte of the access sequence (see Figure 6-11).
On SRAM read access, one or more bytes of read data are transferred on MISO
starting with the third byte of the access sequence (see Figure 6-12).
As long as SEL is logic low, every subsequent byte read or write increments the
address counter of the Frame Buffer until the SRAM access is terminated by setting
Figure 6-13 and Figure 6-14 illustrate an example SPI sequence of a SRAM access to
write and read a data package of 5 byte length respectively.
XX
SEL = H.
DATA 1
XX
DATA 2
XX
DATA 3
XX
DATA 4
XX
AT86RF230
DATA 5
XX
15
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