BCM567X BOARDCOM [Broadcom Corporation.], BCM567X Datasheet - Page 22

• Manufacturer Part Number: BCM567X
• Description: A Scalable Approach to Gigabit Ethernet Switch Design
• Manufacturer: BOARDCOM [Broadcom Corporation.]

BCM567x/BCM569x
White Paper
06/27/02
R
/R
P
L
ESILIENCY
EDUNDANCY AT THE
ORT
EVEL
Enterprise customers are requiring near-100% uptime in their network equipment now, as data applications grow
increasingly mission-critical and voice traffic (for which businesses have virtually no tolerance for downtime) joins the LAN.
There are several ways that the StrataXGS architecture addresses this requirement. First, the BCM5670 has a redundant
link so that system vendors can connect different ports across multiple paths.
Designers can also build a dual-chip configuration and trunk ports between two StrataXGS chips. When both connections
are up and running, traffic can be shared between the two connections. However, if one connection should fail, traffic will
automatically fail over to the live chip. This function is in full compliance with the IEEE 802.3ad specification for trunking.
Port mirroring is also supported; activity on a particular port can be copied onto another designated port, to which a sniffer
can be attached for debugging and running diagnostics. This enables problems to be addressed without having to take any
components out of commission while doing so, contributing considerably to system uptime.
P
ERFORMANCE
The StrataXGS architecture, as mentioned, allows for nonblocking, wire-speed performance because the aggregate
bandwidth in the backplane is greater than the sum of the incoming ports. Activating any number of intelligent features, such
as QoS, does not affect performance, which is 32 million packets per second (pps) across the backplane.
Another feature that contributes to high-end performance is support for dual trunking, which enables traffic load sharing.
StrataXGS also prevents head-of-line (HOL) blocking to boost throughput. To prevent HOL blocking, when an egress port
is congested because of Class of Service (CoS) markings, packets destined to that port are dropped at ingress.
Flow control mechanisms are also at work to enhance performance. The system can send out “pause” frames when the
number of packets for a given port exceeds a predefined threshold. These features also are contributing factors to QoS.
T
P
M
RAFFIC
RIORITIZATION AND
ANAGEMENT
IETF Differentiated Services (DiffServ)-compliant CoS capabilities enable systems built on the StrataXGS architecture to
mark Differentiated Services Code Point (DSCP) bits in order to classify a frame, then take action on the frame based on
that class. The Broadcom ContentAware™ classification engine in the StrataXGS chips allows for wire-speed Layer 2
through Layer 7 classification and management. This means that treatment of packets through the switch can be determined
based on the application type.
The Broadcom-patented Fast Filter Processor™ (FFP) enables switches to take action on the frames according to “if/then”
scenarios. For example, a specific packet could be dropped, have its priority changed, or be steered to a specific port number
in the event that certain network conditions exist. All the packet inspection, filtering, trapping, modification, and steering
performed by the FFP takes place at wire speed. FFP-enabled packet treatments require some customization on the part of
the switch designer.
QoS capabilities in the StrataXGS family also include metering/rate limiting to put a ceiling on the amount of network
bandwidth that any one application, protocol, or user can consume. The StrataXGS components can inspect a transmission
up to 80 bytes deep at wire speed and can control bandwidth on each port to a 1 Mbps granularity. Systems vendors can
write software specifying what frames to recognize and what action to take on those frames. StrataXGS supports QoS-
awareness of all enterprise network components, including 802.11x wireless access points and VoIP phones that may be
connected to an Ethernet segment.
Packets destined for the CPU can have a separate priority than the rest of the ports; four priority classes are defined. Packets
headed to CPU can be selectively enabled or disabled.
Bro adco m C orp or atio n
Page
16 StrataXGS Features and Benefits in Depth
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