HI-15530CDM HOLTIC [Holt Integrated Circuits], HI-15530CDM Datasheet - Page 3

• Manufacturer Part Number: HI-15530CDM
• Description: Manchester Encoder / Decoder
• Manufacturer: HOLTIC [Holt Integrated Circuits]

ENCODER OPERATION
The encoder requires a single clock with a frequency of
twice the desired rate applied at the SEND CLOCK input.
An auxiliary divide by six counter is provided on chip which
can be utilized to produce the SEND CLOCK by dividing
the ENCODER CLOCK.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA input with every low-to-high
transition of the ENCODER SHIFT CLOCK (3) - (4). After
the sync and the Manchester II coded data are transmitted
through the
the Encoder adds on an additional bit which is the parity for
that word (5). If ENCODER ENABLE is held high continu-
ously, consecutive words will be encoded without an
interframe gap. ENCODER ENABLE must go low by time
(5) as shown to prevent a consecutive word from being
encoded. At any time a low on the
will force both bipolar outputs to a high state but will not
affect the Encoder in any other way.
SYNC SELECT
SEND DATA
SHIFT CLK
ZERO OUT
SEND CLK
ENCODER
ENCODER
ONE OUT
BIPOLAR
BIPLOAR
ENABLE
DATA IN
SERIAL
TIMING
BIPOLAR ONE
(1) (2)
and
VALID
SYNC
SYNC
BIPOLAR ZERO
0
OUTPUT INHIBIT
1
SYNC
SYNC
HOLT INTEGRATED CIRCUITS
(3)
2
15
DON’T CARE
DON’T CARE
15
15
3
outputs,
14
14
14
4
input
13
13
13
3
HI-15530
5
12
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low to high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new
word.
12
12
6
MASTER RESET
MASTER RESET
SEND CLK IN
SEND CLK IN
ENCODER CLK
ENCODER CLK
11
6 OUT
6 OUT
11
11
7
10
Counter
Counter
6 6
6 6
3
SEND
SEND
DATA
DATA
Bit
Bit
15
3
3
2
16
2
2
ENCODER
ENCODER
SHIFT
SHIFT
1
CLK
CLK
17
1
1
0
18
(4) (5)
SERIAL
SERIAL
0
0
DATA
DATA
IN
IN
ENCODER
ENCODER
19
P
P
ENABLE
ENABLE
Character
Character
Former
Former
OUTPUT
OUTPUT
SELECT
SELECT
INHIBIT
INHIBIT
SYNC
SYNC
ZERO OUT
ZERO OUT
BIPOLAR
BIPOLAR
ONE OUT
ONE OUT
BIPOLAR
BIPOLAR