MT9075 MITEL [Mitel Networks Corporation], MT9075 Datasheet - Page 60

• Manufacturer Part Number: MT9075
• Description: E1 Single Chip Transceiver
• Manufacturer: MITEL [Mitel Networks Corporation]

MT9075A
4-188
7-0
Bit
Bit
(Page 0BH & 0CH, Address 17H) (continued)
7
6
5
4
3
Table 87 - HDLC Interrupt Status Register
Table 86 - HDLC Interrupt Mask Register
Txunder,
EOPD,
EOPR,
RxFf &
TEOP,
RxOvfl
EOPD
EOPR
Name
Name
TEOP
TxFL
TxFl,
Ga,
FA:
(Pages 0BH & 0CH, Address 16H)
GA
This register is used with the
Interrupt Register to mask out the
interrupts that are not required by
the microprocessor. Interrupts that
are masked out will not produce an
IRQ; however, they will set the
appropriate bit in the Interrupt
Register. An interrupt is disabled
when the microprocessor writes a 0
to a bit in this register. This register
is cleared on power reset.
Go-Ahead. Indicates a go-ahead
pattern was detected by the HDLC
receiver. This bit is reset after a
read.
End Of Packet Detect. This bit is
set to one when an end of packet
(EOP) byte was written into the RX
FIFO by the HDLC receiver. This
can be in the form of a flag, an abort
sequence or as an invalid packet.
This bit is reset after a read.
Transmit End Of Packet. This bit is
set to one when the transmitter has
finished sending the closing flag of a
packet or after a packet has been
aborted. This bit is reset after read.
End Of Packet Read. This bit is set
to one when the byte about to be
read from the RX FIFO is the last
byte of the packet. It is also set to
one if the Rx FIFO is read and there
is no data in it. This bit is reset after
a read.
TX FIFO Low. This bit is set to one
when the TX FIFO is emptied below
the selected low threshold level.
This bit is reset after a read.
Functional Description
Functional Description
7 - 0 Crc15-8 The MSB byte of the CRC received
Bit
Bit
2
1
0
Table 87 - HDLC Interrupt Status Register
Txunder
Table 88 - Receive CRC MSB Register
RxOvfl
Name
Name
(Page 0BH & 0CH, Address 17H)
RxFf
FA:
(Pages 0BH & 0CH, Address 18H)
from the transmitter. These bits are
as the transmitter sent them; that is,
most
inverted. This register is updated at
the end of each received packet and
therefore should be read when end
of packet is detected.
Frame Abort/TX FIFO Underrun.
When Intsel bit of Control Register 2
is low, this bit is set to one when a
frame abort is received during pack-
et reception. It must be received af-
ter a minimum number of bits have
been received (26) otherwise it is ig-
nored.
When Intsel bit of Control Register
2 is one, this bit is set to one for a
TX FIFO underrun indication. If one
it indicates that a read by the
transmitter was attempted on an
empty Tx FIFO.
This bit is reset after a read.
RX FIFO Full. This bit is set to one
when the RX FIFO is filled above
the selected full threshold level.
This bit is reset after a read.
RX FIFO Overflow. A one indicates
that
overflowed (i.e. an attempt to write
to a 128 byte full RX FIFO). The
HDLC will always disable the
receiver once the receive overflow
has been detected. The receiver
will be re-enabled upon detection of
the next flag, but will overflow again
unless the RX FIFO is read. This bit
is reset after a read.
Preliminary Information
Functional Description
Functional Description
the
significant
128
byte
bit
RX
first
FIFO
and