SPT9691SCC ETC [List of Unclassifed Manufacturers], SPT9691SCC Datasheet - Page 4

• Manufacturer Part Number: SPT9691SCC
• Description: WIDE INPUT VOLTAGE, JFET COMPARATOR
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Figure 1 - Timing Diagram
SWITCHING TERMS (Refer to figure 1)
t
t
t
t
SPT
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
pdH
pdL
pLOH
pLOL
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage ( the input offset voltage) to the
50% point of an output LOW to HIGH transition.
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage ( the input offset voltage) to the
50% point of an output HIGH to LOW transition.
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t
and held; those occurring after t
Latch Enable
Latch Enable
Input Voltage
Differential
Output Q
Output Q
V
IN
+=300 mV,
H
will not be detected. Changes between t
t
V
t
pdH
S
OD
V
OD
=150 mV
t
pdL
t
H
4
t
pLOH
t
pLOL
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of t
maintained for a time t
edge and LE rising edge and held for time t
edge for the comparator to accept data. After t
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t
tion, and the output transitions occur after a time of t
t
t
t
t
V
pLOL
H
pL
S
OD
.
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
tpL
pdL
or t
S
pdH
and t
s
(set-up time) before the LE falling
(Q or Q ). The input signal must be
H
50%
V Ref ± V OS
50%
50%
may not be detected.
pL
is needed for strobe opera-
s
will be detected
H
after the falling
H
, the output
SPT9691
pLOH
10/6/97
or