AK4121A AKM [Asahi Kasei Microsystems], AK4121A Datasheet
AK4121A
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AK4121A Summary of contents
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... The AK4121A is a stereo asynchronous sample rate converter. The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Since the internal PLL eliminates the need for a master clock in slave mode, the AK4121 simplifies the system design. ...
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... IDIF1 IDIF2 ■ Difference between AK4121 and AK4121A The AK4121A has a better performance than the AK4121 regarding of the tracking capability to the change of the input sampling frequency (FSI) which normally takes long settling time. Refer to “Tracking to the Input Sampling Frequency”. MS0337-E-02 24pin VSOP (0 ...
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... MS0337-E-02 PIN/FUNCTION Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When “L”, the AK4121A is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input ...
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Note 1) Parameter Power Supplies: Core Input Buffer |AVSS-DVSS| Input Current, Any Pin Except Supplies Input Voltage Ambient Temperature (Power applied) Storage Temperature Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may ...
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VDD=3.0∼3.6V; TVDD=3.0~5.5V) Parameter Digital Filter Passband −0.001dB 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 0.452 ≤ ...
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... Power-down & Reset Timing PDN Pulse Width Note 8. Min is 8kHz when BYPASS=“H”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121A must be reset by bringing PDN pin “H” to “L” upon power-up. MS0337-E-02 SWITCHING CHARACTERISTICS =20pF) ...
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Timing Diagram MCLK LRCK BICK LRCK tBLR BICK tLRS SDTO SDTI MS0337-E-02 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Figure 1. Clock Timing tLRB tSDS tSDH Figure 2. Audio Interface Timing at Slave Mode - 7 - VIH VIL ...
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LRCK BICK SDTO PDN Note 11. BICK means IBICK and OBICK. Note 12. LRCK means ILRCK and OLRCK. MS0337-E-02 tMBLR Figure 3. Audio Interface Timing at Master Mode tPD Figure 4. Power-down & Reset Timing - 8 - 50%VDD dBCK ...
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System Clock The input port works in slave mode only. The output port works in slave and master mode. An internal system clock is created by the internal PLL using ILRCK. The MCLK is not needed when the output ...
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LRCK BICK (64fs) SDTI Don’t care 16bit 15:MSB, 0:LSB SDTI 19 Don’t care 20bit 19:MSB, 0:LSB LRCK BICK (64fs) SDTI 19 18 20:MSB, 0:LSB LRCK BICK (64fs) SDTI 19 18 ...
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Soft Mute Operation When the SMUTE pin changes to “H”, the output signal is attenuated from 0dB to − ∞dB during 1024 OLRCK cycles. When the SMUTE pin returns to “L”, the attenuation is cancelled and the output signal ...
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... System Reset Bringing the PDN pin=“L” places the AK4121A in the power-down mode and initializes the digital filter. This reset should always be done after power-up. When the PDN pin = “L”, the SDTO output is “L”. Regarding the SDTO valid time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs “ ...
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... Internal Reset Function for Clock Change The AK4121A is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. ■ Sequence of changing clocks The recommended sequence for changing clocks is shown in Figure 10. External clocks state 1 ...
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... The AK4121A requires careful attention to power supply and grounding arrangements. VDD are usually supplied from the system’s analog supply. AVSS and DVSS of the AK4121A must be connected to the analog ground plane. System analog ground and digital ground should be connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors especially a 0.1μ ...
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... Jitter Tolerance Figure 12 shows the jitter tolerance to ILRCK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 12. When the jitter amplitude is 0.01UIpp or less, the AK4121A operates normally regardless of the jitter frequency. 10.00 1.00 0.10 (2) 0.01 0.00 1 (1) Normal operation (2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.) (3) There is a possibility that the output data is lost ...
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... IBICK ODIF1 ODIF0 SDTI CMODE2 IDIF0 CMODE1 IDIF1 IDIF2 CMODE0 10u + 0.1u 1.0n VDD FILT AVSS DVSS PDN TVDD MCLK SMUTE OLRCK DEM0 AK4121A DEM1 OBICK ILRCK SDTO IBICK ODIF1 ODIF0 SDTI CMODE2 IDIF0 CMODE1 IDIF1 IDIF2 CMODE0 - 16 - +3.3V Analog 0.1u +3.3~5V Digital (*1) fso DSP2 +3.3V Analog 0.1u +3 ...
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VSOP (Unit: mm) *7.9 ± 0 0.22 ± 0.1 Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0337-E-02 PACKAGE ...
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... Date (YY/MM/DD) Revision 04/09/01 00 07/06/05 01 07/07/25 02 MS0337-E-02 MARKING AKM AK4121AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code REVISION HISTORY Reason Page Contents First Edition SRC PERFORMANCE Error Correct 4 Dynamic Range, Worst Case FSO/FSI=32kHz/44.1kHz → 48kHz/96kHz SWITCHING CHARACTERISTICS Audio Interface timing Description ILRCK Edge to IBICK “↑” is changed to ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status ...