CXP85112 Sony Corporation, CXP85112 Datasheet
CXP85112
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CXP85112 Summary of contents
Page 1
... Iines (more than 4 Iines possible) Double scan mode compatible, jitter elimination circuit ...
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... CXP85112B/85116B, CXP85220A/85224A/85228A/85232A – 2 – ...
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... PC0 PD7/EC 25 PD6/RMC 26 PD5/ACI 27 PD4/HSI 28 PD3/SI 29 PD2/ PD1/SCK Note (Pin 63) must be connected to V CXP85112B/85116B, CXP85220A/85224A/85228A/85232A 2. Vss for both Pins 32 and 62 must be grounded (Pin 61) must be connected to GND. – 3 – PF0/PWM0 59 PF1/PWM1 58 PF2/PWM2 57 ...
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... PC5 PC4 14 PC3 15 PC2 16 PC1 17 PC0 18 19 PD7/EC Note (Pin 56) must be connected to V CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Vss for both Pins 26 and 58 must be grounded (Pin 55) must be connected to GND. – 4 – ...
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... PF7/PWM7/ I/O SDA1 BLK Output HSYNC Input VSYNC Input CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. ...
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... RST I/O MP Input V DD Vss CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Description Clock oscillation I/Os for CRT display. Oscillation frequency is set using the external L and C. Crystai connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. RST is an I/O, from whlch Low level is output when the built-in power-on reset function is activated at the rise of power on ...
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... Data bus INT2, SI, HSI, ACI, RMC pins Port D SCK or SO Output eneble PD1/SCK PD2/SO Data bus 2 pins CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Circuit format Data for Ports A, B, and C Direction for Ports A, B, and C RD (Ports A, B, and C) Port D data Port D direction RD (Port D) ...
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... C output enable PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ Port F data SDA1 Port selection SCL, SDA 2 ( circuit) 4 pins CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Circuit format Schmitt input IP RD (Port E) Input multiplexer IP Data bus RD (Port E) TO, PWM PWM SCL, SDA PWM Schmitt input – 8 – ...
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... EXLC EXLC XLC XLC 2 pins EXTAL EXTAL XTAL XTAL 2 pins RST Mask option 1 pin MP 1 pin CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Circuit format Schmitt input IP Input polarity IP Oscillation control IP • Diagram shows IP • Feedback resistor Pull-up resistance Schmitt input OP From power-on reset circuit (Mask option) ...
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... Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP. 3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST. 4 Specifies only during external clock input. CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Symbol Rating V –0 – ...
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... RST specifies input current when the pull-up resistance has been selected; Ieakage current when no resistance has been selected. 3 Specifies only when the oscillatlon of OSD has been terminated. 4 This device does not enter the stop mode. CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Pins Conditions V = 4.5V PD, PE6, PE7, ...
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... EXTAL Crystal oscillation Ceramic oscillation EXTAL CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (Ta = –20 to +75°C, V Pins Conditions XTAL Fig. 1, Fig. 2 EXTAL , Fig. 1, Fig. 2 EXTAL ...
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... SCK ) t SCK SO delay time KSO Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. SCK SI SO CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (Ta = –20 to +75°C, V Pins Conditions Input mode SCK Output mode SCK input mode SCK SCK output mode ...
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... Power on reset Item Symbol Pins Power supply rise time Power supply cut-off time Specifies only when the power-on reset function has been selected The power supply should be raised smoothly. CXP85112B/85116B, CXP85220A/85224A/85228A/85232A = 4.5 to 5.5V, Vss = 0V reference) DD Symbol Pins Conditions Min. t INT0 INT2 IL t ...
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... A, ADD LSR A LSR A LSR A LSR A ADC A, #00H CMP A, #10H BNE ADC_SKIP ; MOV A, #0FH ADC_SKIP: CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (Ta = –20 to +75°C, V Pin Condition Ta = 25° 5.0V DD Vss = 0V AN0 to AN3 Value at which the digital conversion value changes ZT from Value at which the digital conversion value changes ...
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... Fig. 10. Recommended circuit example for I • Pull-up resistors (R ) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). P • Serial resistance (Rs = 300Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flashover. CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (Ta = –20 to +75°C, V Symbol Pins f SCL ...
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... VSYNC after-edge rise time/fall time * H indicates 1HSYNC period. HSYNC when Bit 5 of OPOL register (01FB ) is set to "0" H VSYNC when Bit 4 of OPOL register (01FB ) is set to "0" H CXP85112B/85116B, CXP85220A/85224A/85228A/85232A = 4.5 to 5.5V, Vss = 0V reference) DD Symbol Pins Condition EXLC Fig OSC XLC t Fig. 11 ...
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... MFG CST4.00MGW CO., LTD. CST4.19MGW RIVER ELETEC HC-49/U03 CORPORATION KINSEKI HC-49/U (-S) LTD. Indicates types with on-chip grounding capacitance (C Mask option table Item Reset pin pull-up resistance Power-on reset circuit CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (ii) EXTAL XTAL XTAL Fig. 13. Recommended Oscillation circuit Model fc (MHz) C (pF ...
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... V – Supply voltage [V] DD OSD oscillation vs. C Calculated curves (reference value by theoretical calculation) 100 10 1 fosc = – Capacitance [pF CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (V 12 1/2 frequency 11 demultiplication mode 10 1/4 frequency demultiplication mode 9 8 1/16 frequency demultiplication mode Sleep mode ...
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... Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE 52 64 SONY CODE EIAJ CODE JEDEC CODE CXP85112B/85116B, CXP85220A/85224A/85228A/85232A 64PIN SDIP (PLASTIC) + 0.4 57.6 – 0 1.778 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SDIP-64P-01 LEAD MATERIAL SDIP064-P-0750 PACKAGE MASS 64PIN QFP(PLASTIC) 23.9 ± ...