AS3910-BQFP AMSCO [austriamicrosystems AG], AS3910-BQFP Datasheet - Page 20

• Manufacturer Part Number: AS3910-BQFP
• Description: 13.56 MHz RFID Reader IC, ISO-14443 A/B
• Manufacturer: AMSCO [austriamicrosystems AG]

AS3910
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
In case an interrupt from a certain source is not required it can be disabled by setting corresponding bit in the Mask Interrupt Register. In case of
masking a certain interrupt source the interrupt is not produced, but the source of interrupt bit is still set in Interrupt Register.
After reading the Interrupt Register the 13.56MHz clock coming from the oscillator is used to produce a reset signal which clears it and resets
INTR signal. Practically in all interrupt cases the oscillator is running when an interrupt is produced. The only exception is the interrupt in the
Initial NFC Target mode where only the Target Activation Detector is operating. In this case the interrupt is cleared with first SCLK rising edge
following reading of the Interrupt Register (an extra dummy CLK pulse during reading of the Interrupt Register or first SCLK pulse of the next SPI
command will do the job).
Table 8. Serial Peripheral Interface (4-wire Interface) Signal Lines
8.9.9 FIFO Water Level and FIFO Status Register
The AS3910 contains a 32 byte FIFO. In case of transmitting the Control logic shifts data which was previously loaded by the external
microcontroller to the Framing Block and further to the Transmitter. During reception, the demodulated data is stored in the FIFO and the external
microcontroller can download received data once reception was terminated.
Transmit and receive capability the AS3910 is not limited by of the FIFO size due to a FIFO water level interrupt system. During transmission an
interrupt is sent (interrupt due to FIFO water level) when the content of data in the FIFO which still need to be sent is lower then the FIFO water
level for receive. The external microcontroller can now add more data in the FIFO. The same stands for receive mode. In case the number of
received bytes gets over the FIFO water level for receive an interrupt is sent to inform the external controller that data has to be downloaded from
FIFO.
The external controller has to serve the FIFO faster then data is transmitted or received. A general rule is that the SCLK frequency has to be at
least double then the actual data rate in receive or transmit.
There are two settings of the FIFO water level available for receive and transmit in Configuration Register 5 (#05).
After data is received the external microcontroller needs to know how long the receive data string was before downloading data from the FIFO:
This information is available in the FIFO Status Register (#09) which displays number of bytes in the FIFO which were not read out.
The FIFO Status Register also contains a FIFO overflow bit. This bit is set when during reception the external processor did not react on time
and more then 32 bytes were written in FIFO. The received data is of course lost in such a case.
8.10 Direct Commands
Table 9. Direct Commands
www.austriamicrosystems.com/HF_RFID_Reader/AS3910
000001
000010
000100
000101
000110
001000
001001
001010
010000
010001
010010
010011
000111
Code
Name
INTR
NFC transmit with Response RF Collision
NFC transmit with Response RF Collision
NFC transmit with Initial RF Collision
Transmit without CRC
Unmask receive data
Avoidance with n=0
Transmit with CRC
Mask receive data
Transmit REQA
Transmit WUPA
Measure RF
Command
AD convert
Set default
Avoidance
Avoidance
Clear
Digital Output
Signal
Puts the AS3910 in default state (same as after power-up)
Stops all activities and clears FIFO
Starts a transmit sequence using automatic CRC generation
Starts a transmit sequence without automatic CRC generation
Transmits REQA command (ISO-14443A mode only)
Transmits WUPA command (ISO-14443A mode only)
Equivalent to Transmit with CRC with additional RF Collision Avoidance
Equivalent to Transmit with CRC with additional RF Collision Avoidance
Equivalent to Transmit with CRC with additional RF Collision Avoidance
Receive after this command is ignored
Receive data following this command is normally processed (this command has
priority over internal mask receive timer)
A/D conversion of signal on AD_IN pin is performed, result is stored in A/D
Converter Output Register
RF amplitude is measured, result is stored in A/D Converter Output Register
Revision 2.3
Signal Level
CMOS
Comments
Interrupt Output pin
Description
20 - 47