AM29PDS322DB100WMI AMD [Advanced Micro Devices], AM29PDS322DB100WMI Datasheet
AM29PDS322DB100WMI
Related parts for AM29PDS322DB100WMI
AM29PDS322DB100WMI Summary of contents
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Am29PDS322D Data Sheet The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of ...
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DATA SHEET Am29PDS322D 32 Megabit ( 16-Bit) CMOS 1.8 Volt-only (1 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one ...
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GENERAL DESCRIPTION The Am29PDS322D Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. This device is offered in a 48-ball FBGA pack- age. The device is designed to be programmed in sys- tem ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Options Standard Voltage Range: V Max Random Address Access Time (ns) Max Page Address Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM ...
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CONNECTION DIAGRAMS A6 B6 A13 A12 WE# RESET RY/BY# WP#/ACC A17 Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products ...
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PIN DESCRIPTION A0–A20 = 21 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect/ Acceleration Input RESET# = Hardware Reset Pin input ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29PDS322D DEVICE NUMBER/DESCRIPTION Am29PDS322D 32 Megabit ( ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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Page Mode Read The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The Page size ...
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If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed the DC Characteristics table represents the CC3 standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes ...
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Table 3. Am29PDS322DT Top Boot Sector Addresses Sector Address Bank Sector A20–A12 SA0 000000xxx SA1 000001xxx SA2 000010xxx SA3 000011xxx SA4 000100xxx SA5 000101xxx SA6 000110xxx SA7 000111xxx SA8 001000xxx SA9 001001xxx SA10 001010xxx SA11 001011xxx SA12 001100xxx SA13 001101xxx ...
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Table 3. Am29PDS322DT Top Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA44 101100xxx SA45 101101xxx SA46 101110xxx SA47 101111xxx SA48 110000xxx SA49 110001xxx SA50 110010xxx SA51 110011xxx SA52 110100xxx SA53 110101xxx SA54 110110xxx SA55 110111xxx SA56 111000xxx SA57 ...
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Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA15 001000xxx SA16 001001xxx SA17 001010xxx SA18 001011xxx SA19 001100xxx SA20 001101xxx SA21 001110xxx SA22 001111xxx SA23 010000xxx SA24 010001xxx SA25 010010xxx SA26 010011xxx SA27 010100xxx SA28 ...
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Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued) Sector Address Bank Sector A20–A12 SA63 111000xxx SA64 111001xxx SA65 111010xxx SA66 111011xxx SA67 111100xxx SA68 111101xxx SA69 111110xxx SA70 111111xxx Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address Sector Address A20–A12 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ...
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The alternate method intended only for programming equipment requires V on address pin A9 and OE#. ID This method is compatible with programmer routines written for earlier AMD flash devices. Contact an AMD representative for further details. The device is ...
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START RESET (Note 1) Perform Erase or Program Operations RESET Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected (If WP the first or last sector will remain protected). ...
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START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a ...
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V is greater than V CC system must provide the proper signals to the control pins to prevent unintentional writes when V greater than V . LKO Write Pulse “Glitch” Protection Noise pulses of less than ...
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Table 10 shows the address and data requirements for the command sequence. To determine sector protec- tion information, the system must write to the appropri- ...
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Start 555h/AAh 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data# Polling Device Verify Byte? Yes No Increment Last Address Address ? Yes Programming Completed (BA) XXXh/90h XXXh/F0h Figure 4. Unlock Bypass Algorithm December 4, 2006 23569A5 ...
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When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the ...
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The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, ...
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Table 10. Am29PDS322D Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Manufacturer ID 4 555 Device ID (Note 9) 6 555 SecSi Sector Factory 4 555 Protect (Note 10) Sector Group ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Inter-Page Read Current CC I CC1 (Notes Active Write Current ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 11. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C L Note: Diodes are IN3064 or equivalent Figure 13. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted V CC Input 0 0.0 V Figure 14. Input Waveforms and ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t Page Read Cycle PRC t Page Address to Output Delay PACC t t Chip ...
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AC CHARACTERISTICS A20 CE# OE# t WE# High-Z Output Same page Addresses PRC PRC PRC t ACC ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Note program address program data ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t WC Valid PA Addresses t AH CE# OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings t RC Addresses VA t ACC t CE ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for Temporary t RSP Sector/Sector Block Unprotect RESET# ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector group protect For sector group ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2 programming typicals ...
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PHYSICAL DIMENSIONS FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA package xFBD 048 6. 12.00 mm PACKAGE 1.20 0.20 0.94 0.84 12.00 BSC 6.00 BSC 5.60 BSC 4.00 BSC 0.25 0.30 0.35 0.80 ...
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REVISION SUMMARY Revision A (December 4, 2000) Initial release. Revision A+1 (February 16, 2001) Ordering Information Added “U” designator to package marking. Deleted burn-in option. Revision A+2 (August 31, 2001) Autoselect Command Sequence Modified section to point to appropriate tables ...