SM8222 Nippon Precision Circuits Inc, SM8222 Datasheet - Page 3

• Manufacturer Part Number: SM8222
• Description: Caller ID Service IC with Call Waiting
• Manufacturer: Nippon Precision Circuits Inc

PIN DESCRIPTION
N u m b e r
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
OSCOUT
FSKEN
MODE
OSCIN
PDWN
AGND
RDRC
DOUT
N a m e
RDET
CDET
DCLK
STGT
RING
RDIN
GND
VDD
CAP
STD
EST
TIP
GS
DR
INT
IC
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
–
–
I
I
I
I
I
I
I
I
I
Tip input: Connected to the telephone through a protection circuit.
Ring input: Connected to the telephone through a protection circuit.
Input stage amplifier output: Used to select the input amplifier gain
Analog ground: Internal reference voltage (V
Reference voltage capacitor connection. C = 0.1 µF
Ring detect input: Line reversal and ring signal detect input. Connect to detect attenuated ring
signals. Schmitt-trigger input.
Ring detect RC connection: RC network connection to set the ring detect delay time. Open-drain
output and schmitt-trigger input.
Ring detect output: RDRC schmitt-trigger buffer output. LOW when a ring signal is detected.
FSK interface mode select: Demodulated FSK signal output method select.
LOW [Mode = 0]: Demodulated data output and data sync clock output.
HIGH [Mode = 1]: Data output in sync with an external clock.
Crystal oscillator element input: Oscillator element connection between OSCIN and OSCOUT.
Crystal oscillator element output: Oscillator element connection between OSCIN and OSCOUT.
Ground: Connect to system ground.
Test input: Tie LOW for normal operation.
Power-down control: LOW for normal operation. HIGH for device power-down state. When device is
powered-down, AGND, OSCOUT, DCLK, DOUT, INT, CDET are all HIGH. DR also goes HIGH in
mode 0 output. Schmitt-trigger input.
FSK signal output control: Demodulated FSK signal output and carrier detect output control.
Mode 0: DCLK, DOUT, DR, CDET control
Mode 1: DCLK, DOUT, CDET control
FSK signal reception enabled when HIGH.
Signal pins (above) go HIGH when FSKEN is LOW.
FSK interface clock: Demodulated FSK signal output clock.
Mode 0: Clock output in sync with data
Mode 1: Data read clock input
Data output: Demodulated FSK signal output. HIGH-level output when PDWN is HIGH or FSKEN is
LOW, or when CDET is HIGH in receive state.
Data output trigger: Demodulated FSK data timing output. Active-LOW. Becomes active when 8 bits
of data are completed.
Carrier (FSK signal) detect output: Goes LOW when a valid carrier signal is detected.
Interrupt signal output: Goes LOW when either RDET is LOW, DR is LOW or STD is HIGH.
Dual tone indicator output: Goes HIGH if the dual tone detect signal is recognized after the external
RC circuit time delay has elapsed.
Dual tone detect output: Goes HIGH when the dual tone is detected.
Dual tone RC time constant circuit connection: External RC network connection for dual tone signal
detection processing. Sets STD output.
Supply voltage
SM8222A/B
Description
DD
/2) output.
NIPPON PRECISION CIRCUITS—3