LC75816W Sanyo Semicon Device, LC75816W Datasheet
LC75816W
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LC75816W Summary of contents
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... Ordering number : ENN7142 1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers Overview The LC75816E and LC75816W are 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75816E and LC75816W also provide on-chip character display ROM and RAM to allow display systems to be implemented easily ...
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... Package Dimensions unit: mm 3151-QFP100E [LC75816E] 23.2 20.0 0.575 0.65 0.3 0.575 80 81 100 1 21.6 LC75816E, 75816W unit: mm 3181B-SQFP100 1.6 0. 0.1 2.7 0.8 SANYO: QFP100E [LC75816W] 16.0 14.0 1.0 0.5 1.0 0.145 100 1 25 0.2 0.1 1.4 0.5 0.5 SANYO: SQFP100 No. 7142-2/43 ...
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... KI4 KI5 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VSS TEST OSCO OSCI INH 100 LC75816E, 75816W LC75816E (QFP100E) LC75816W (SQFP100 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 ...
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Specifications Absolute Maximum Ratings 25°C, V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Allowable Operating Ranges –40 to +85°C, V Parameter Symbol V DD ...
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Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Hysteresis V H Power-down detection voltage V DET Input high level current I IH Input low level current I IL Input floating voltage V IF Pull-down resistance R PD Output off ...
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When CL is stopped at the low level CE tøH VIH1 50% CL VIL1 VIH1 DI VIL1 tds tdh DO • When CL is stopped at the high level CE tø tds DO Block Diagram VLCD CONTRAST ...
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... Pin Functions Pin No. Pin LC75816E LC75816W S1 to S63 Segment driver outputs. S64/COM10 66 64 The S64/COM10, S65/COM9 pins can be used as common driver output under the “set display technique” instruction. S65/COM9 67 65 COM1 to COM8 Common driver outputs. ...
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Block Functions • AC (address counter counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. • DCRAM (data control RAM) DCRAM is RAM ...
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ADRAM (Additional data RAM) ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 13 display data is displayed directly without the use of CGROM or CGRAM. The table below lists the ...
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Serial Data Input • When CL is stopped at the low level • When CL is stopped at the high level ...
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LC75816E, 75816W No. 7142-11/43 ...
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Detailed Instruction Descriptions • Set display technique ... <Sets the display technique> Code D56 D57 D58 D59 D60 D61 D62 D63 DT1 DT2 don’t care DT1, DT2: Sets the display technique DT1 DT2 Display ...
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SC: Controls the common and segment output pins SC Common and segment output pin states 0 Output of LCD drive waveforms 1 Fixed at the V 4 level (all segments off) LCD Note: *13. When the S1 ...
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DCRAM data write ... <Specifies the DCRAM address and stores data at that address> D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 AC0 AC1 AC2 AC3 AC4 ...
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Data format at (1) (24 bits) D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 ...
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IM: Sets the method of writing data to ADRAM IM 0 Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) 1 Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is ...
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CGRAM data write ... <Specifies the CGRAM address and stores data at that address> CD1 CD2 CD3 CD4 CD5 D16 D17 D18 D19 D20 CD17 CD18 CD19 CD20 CD21 D32 D33 D34 D35 D36 ...
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Set display contrast ... <Sets the display contrast> D48 D49 D50 D51 D52 CT0 CT1 CT2 CT3 X CT0 to CT3: Sets the display contrast (11 steps) CT0 CT1 CT2 CT3 LCD drive 4/4 bias voltage supply V 0 ...
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Set key scan output port/general-purpose output port state ... <Sets the key scan output port and general-purpose output port states> D48 D49 D50 D51 D52 KC1 KC2 KC3 KC4 KC5 KP1, KP2: These bits switch the functions of the ...
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Serial Data Output • When CL is stopped at the low level • When CL is stopped at the high level ...
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Output Data • KD1 to KD30 : Key data When a key matrix keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is ...
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Key Scan Operation Functions • Key scan timing The key scan period is 2304T(s). To reliably determine the on/off state of the keys, the LC75816E/W scans the keys twice and determines that a key has been pressed when the key ...
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In sleep mode The pins KS1 to KS6 are set to high or low with the "set key scan output port/general-purpose output port state" • instruction key on one of the lines corresponding to a KS1 to ...
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Duty, 1/4 Bias Drive Technique COM1 COM2 COM8 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output ...
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Duty, 1/4 Bias Drive Technique COM1 COM2 COM9 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output ...
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Duty, 1/4 Bias Drive Technique COM1 COM2 COM10 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output ...
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Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or ...
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V DD VDET V LCD Instruction execution Disabled Key scan General-purpose Fixed at the low level (V output ports Display state “Set key scan output port/general-purpose output port state” instruction execution LC75816E, 75816W Initial state settings Execution enabled ...
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Block states during a system reset (1) CLOCK GENERATOR, TIMING GENERATOR When a reset is applied, the oscillator on the OSCI, OSCO pins is started forcibly. This generates the base clock and enables instruction execution. (2) INSTRUCTION REGISTER, INSTRUCTION ...
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COMMON DRIVER VLCD CONTRAST ADJUSTER VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VDD TIMING VDET GENERATOR VSS GENERATOR TEST 3. Output pin states during the reset period Output pin State during reset S1 to S63 LCD 21 S64/COM10, S65/COM9 ...
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Sample Application Circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) +5V VDD *24 TEST VSS +8V VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 C ≥ 0.047 µF OSCI OSCO INH From the ...
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Sample Application Circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) +5V VDD *24 TEST VSS +8V VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 VLCD4 C ≥ 0.047 µF OSCI 10 ...
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Sample Application Circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) +5V VDD *24 TEST VSS +8V VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 OSCI C ≥ 0.047 µF OSCO INH From the ...
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Sample Application Circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) +5V VDD *24 TEST VSS +8V VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 VLCD4 C ≥ 0.047 µF OSCI 10 ...
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Sample Application Circuit 5 1/10 duty, 1/4 bias drive technique (for use with normal panels) +5V VDD *24 TEST VSS +8V VLCD OPEN VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 C ≥ 0.047 µF OSCI OSCO INH From the ...
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Sample Application Circuit 6 1/10 duty, 1/4 bias drive technique (for use with large panels) +5V VDD *24 TEST VSS +8V VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 VLCD4 C ≥ 0.047 µF OSCI 10 ...
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Sample Correspondence between Instructions and the Display (When the LC75816-8722 is used) Instruction (hexadecimal) LSB No. D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 Power application 1 (Initialization with the ...
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Continued from preceding page. Instruction (hexadecimal) LSB No. D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 Set AC address Display on/off control ...
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Notes on the controller key data read techniques 1. Timer based key data acquisition • Flowchart YES Key data read processing • Timing chart Key on Key input Key scan ...
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Interrupt based key data acquisition • Flowchart YES Key data read processing Wait for at least t10 YES Key off • Timing chart Key on Key ...
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Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low low, the controller recognizes that a key ...
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LC75816E, 75816W No. 7142-42/43 ...
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Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as ...