HDSP-390X Agilent(Hewlett-Packard), HDSP-390X Datasheet - Page 20

• Manufacturer Part Number: HDSP-390X
• Description: 20 mm (0.8 inch) Seven Segment Displays
• Manufacturer: Agilent(Hewlett-Packard)

Rx I/O Definition (cont’d.)
592
ECLGND
EQEN
ERROR
FCLK
FDIS
FF
FLAG
FLAGSEL
GND
HGND
Name
Pin
32
52
53
72
19
40
75
20
39
45
34
23
24
33
43
44
63
64
73
78
13
5
O-ECL
O-ECL
O-ECL
O-ECL
I-ECL
I-ECL
I-ECL
Type
S
S
S
ECL Ground: Normally 0 volts. This ground is used for the ECL pad
drivers. For best performance it is suggested that coupling of the noisy
ECLGND to the clean GND and HGND grounds be minimized.
Enable Input for Cable Equalization: When asserted, this signal
activates the cable equalization amplifier on the DIN, DIN* serial
data inputs.
Received Data Error: Asserted when a frame is received that does
not correspond to either a valid Data, Control, or Fill frame encoding.
When FLAGSEL is not active, the Rx chip also tests for strict
alternation of flag bits during data frames. A flag bit alternation
error will also cause an ERROR indication.
Frame Clock Monitor: Leave unterminated in normal use.
Frequency Detector Disable Input: When active, this input
disables the Rx PLL Frequency detector and enables a phase detector.
The Frequency detector is used during the start-up sequence to
acquire wide-band lock on Fill Frames, but must be disabled prior to
sending data patterns. This input is normally controlled by the Rx
state machine.
Fill Frame Status: During a given STRBOUT clock cycle, if neither
DAV, CAV, or ERROR are active, then the currently received frame
is a Fill frame. The type of fill frame received is indicated by the FF
pin. If FF is low, then FF0 has been received. If FF is high, then
either FF1a or FF1b has been received.
Flag Bit: If both Tx and Rx have FLAGSEL asserted, this output
indicates the value of the transmitted flag bit, then this received bit
can be treated just like an extra data bit. If both Tx and Rx have
FLAGSEL set to low, FLAG is used to differentiate the even frame
from the odd frame in the line code.
Flag Bit Mode Select: When this input is high, the extra FLAG bit
output is effectively an extra transparent data bit. Otherwise, the
FLAG bit is checked for alternation during data frames. Any break in
strict alternation results in an ERROR indication to the user.
Ground: Normally 0 volts. This ground is used for all the core logic
other than the output drivers.
High Speed Ground: Normally 0 volts. This ground is used to
provide clean references for the high speed DIN, DIN*, LIN, LIN*,
TCLK, TCLK* inputs.
Signal