LC78626 Sanyo Semicon Device, LC78626 Datasheet
LC78626
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LC78626 Summary of contents
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... Ordering number : EN5692 Overview The LC78626E is a monolithic compact disk player signal processing and servo control CMOS IC equipped with an internal anti-shock control function. Designed for total functionality including support for EFM-PLL, and one-bit D/A converter, and containing analog low-pass filter, the LC78626E provides optimal cost-performance for low-end CD players that provide anti-shock systems ...
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... Up to ten seconds of skip prevention (when using 4M of DRAM) through ADPCM compression/decompression processing. 1M/4M bit DRAM can be selected. • Memory overflow detection output. • Free memory output. LC78626E Features • 100-pin QFP • A single 3.2 V/5 V power supply No. 5692-2/32 ...
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... Equivalent Circuit Block Diagram LC78626E No. 5692-3/32 ...
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... Pin Assignment LC78626E Top view No. 5692-4/32 ...
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... Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Range of operating frequencies Crystal oscillator frequency Electrical Characteristics 25°C, V Parameter Consumption current Input high level current. LC78626E = 0V SS Symbol Conditions V max ...
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... Total harmonic distortion rate Dynamic range Signal to noise ratio Cross talk Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit. LC78626E Symbol Conditions DEFI, EFMI, HFL, TES, RWC, COIN, CQCK, FMT, MR1, RES, TESE, TESD, WOK, ...
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... LC78626E Figure 1 Command Input Figure 2 Subcode Q Output Figure 3 Subcode Output No. 5692-7/32 ...
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... LC78626E Figure 4 General Port Input Timing Figure 5 General Port Output Timing No. 5692-8/32 ...
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... General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as an input 33 CONT2 I/O port and connect set this as an output port and leave it open. LC78626E Function Test input. Equipped with internal pull-down resistor. Must be connected to 0V. External VCO control phase comparator output. Internal VCO ground. Must be connected ...
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... EMPP O DRAM empty (an RZP pulse is output when the DRAM is empty). 69 RES I External reset input: low reset (all internal blocks are reinitialized). LC78626E Description L channel mute output. L channel power supply. L channel output. L/R channel ground. Must be connected channel output. R channel power supply. ...
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... Digital system ground. Must be connected AD4 O DRAM address bus 96 AD3 O DRAM address bus 97 AD2 O DRAM address bus 98 AD1 O DRAM address bus 99 AD0 O DRAM address bus 100 V P Digital system power supply. DD LC78626E Description high: detection complete. (DRAM write start). high: detection start. No. 5692-11/32 ...
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... The EFM signal goes high when the frame sync signal (the true sync signal) from the PCK matches the timing (the interpolated sync signal) generated by the counter. This serves as the sync detect monitor (holding the high level over a single frame). LC78626E Pin 18: EFMI, Pin 17: EFMO, Pin 1: DEFI, and Pin 20: CLV When an HF signal is input to the EFMI, an EFM signal (NRZ), sliced at the optimal levels, is obtained ...
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... Resets the command input noise reduction mode. This command makes it possible to reduce the noise that is mixed into the CQCK clock. This is effective for noise of less than 500 ns; however, the CQCK timing must be set to have 1 µs or more for t LC78626E Single-byte commands Two-byte command (two sets of RWC). ...
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... DISC 8 cm Set $A9 DISC 12 cm Set When the internal mode is the rough servo, the CLV control gain for the 8 cm disk can be reduced by 8.5 dB from the level for the 12 cm disk. LC78626E RES = low + – and CLV outputs for each mode are as shown in the table below. ...
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... The CLV 3-state output command makes it possible to control the CLV with a single pin. However, because this will cause the spindle gain to fall by 6 dB, it will be necessary to increase the gain on the servo side. 2-state output 3-state output LC78626E RES = low Phase comparator ...
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... TES signal. However, when the HFL signal is absent because of dust, scratches, etc., there is the danger that there will be no track count pulse, and thus caution is required when using this method. LC78626E RES = low COMMAND RES = low – ...
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... The TOFF pin is only low when the CLV mode is active when related to the disk control mode, and this terminal is high during start, stop, and break control. Moreover, the TOFF pin can be turned on and off independently using commands. However, the disk motor control is only enabled when the CLV mode is active. LC78626E COMMAND The new track jump. ...
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... In the 1 TRACK JUMP #3 command there is no brake period (period c), but rather caution is warranted because it is necessary to generate the brake mode using an external circuit. * Although in the 2TRACK JUMP IN (OUT) of the new track jump mode the brake period (period c) did not exist for the LC78620E/21E/25E ICs, in this IC period C has been changed to 60 ms. LC78626E b c 233 µ 233 µ ...
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... The number of desired track checks = the number of track checks input – 1 Command Track check In/Out command Track check LC78626E COMMAND JP 3-state output COMMAND Track check IN Track check OUT Two byte command reset ...
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... SBSY is a signal output for each subcode block. This signal becomes high during sync signals S0 and S1, and its falling edge indicates the end of the subcode sync signal and the beginning of the data in subcode block (in EIAJ format). LC78626E No. 5692-20/32 ...
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... This IC becomes active when the CS pin is low, and the subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin enters a high impedance state. LC78626E COMMAND ADDRESS FREE ...
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... LRSY. However, when the ATT DATA SET command has been used, then the target value is set directly. When new data is entered during the transition, then the target value is approached from whatever value is in effect at that time. Caution is required when using the step-up/step-down commands at this time. LC78626E COMMAND STO CONT ...
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... The zero cross determination is made in the range where the most significant 7 bits are all “1” or all “0.” Because the MUTE–12 dB command ($02) that was found in the LC78620E and 78621E has been deleted, the digital attenuator is used and ATT DATA = 60 ($3C) is set. LC78626E ATT DATA 100H 44 ...
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... These ports can each be set individual as control output ports by the port I/O set command. The ports are selected by the lower four bits of a single byte. Starting with the least significant bit, these four bits of this single byte data correspond to CONT2, CONT3, CONT4, and CONT5. The command uses a two-byte command format (RWC1 set). LC78626E Correct data Flagged data Interpolated data Held at the previous value ...
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... When using double speed/normal speed playback mode, a 16.9344 MHz signal will be output from the 16M pin after the external crystal oscillator 16.9344 MHz. A 4.2336 MHz will be output constantly from the 4.2M pin, forming a LA9230/40 Series LSI system clock. When OSC is OFF, both terminals are constantly either high or low. LC78626E COMMAND OSC ON ...
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... Forward frequency division –1 589 ±0 588 Standard frequency division +1 587 +2 587 Backwards frequency division +3 587 +4 or greater Forces transition to ± 0 LC78626E START STOP 0dB –∞ Address1 Address Free New New DATA0 DATA 00H to EEH ON OFF Double speed ON OFF ...
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... DRAM was full, and writing to the DRAM is terminated. In this case, the microcontroller should perform the same process as if the DRAM had become full. The Setting pins Pin High FMT Anti-shock mode: ON MR1 1M bit (256K 4 bit) DRAM LC78626E Low Anti-shock mode: OFF 4M bit (1M 4 bit) DRAM No. 5692-27/32 ...
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... The reset is released by setting this pin high. Furthermore, when controlling the independent reset using commands, the ASRES pin must be tied low (connected to 0 V). Code $F4 Independent reset disable (release) $F5 Independent reset enable/inrush LC78626E L point because the DRAM is full Track jump Track jump COMMAND RES = low No. 5692-28/32 ...
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... OUT $3F In the DISC MTR BRAKE command ($06) function, when the internal brake ON mode is on, the function that puts the WRQ pin high is not latched. For details, see the internal brake mode in section 6-(5) on page 16. LC78626E $40 * UBIT ON $41 * UBIT OFF $42 * DOUT ON ...
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... After the PLL DIV (the 1/2 frequency divider for the PLL part) is reset, then this turns OFF. (the opposite of the LC78622E). However, the functions of the commands ($AC, $AD) are the same as for the LC78622E. LC78626E $C0 $C1 * Double speed playback FOCUS START #2 $C2 * Normal speed playback ...
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... Sample Application Circuit LC78626E No. 5692-31/32 ...
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... V 3.0 to 5.5 V 3.0 to 5.5 V QFP80E QFP64E QFP64E LC78625E LC78626E LC78630E Internal VCO Internal VCO Internal VCO FR = 1.2kΩ 5.1kΩ 1.2kΩ 16k 16k 18k –12dB, –∞ –∞ ...