1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Product Features
• Advanced Low Power CMOS Operation
• Can serve as a 5V to 3V translator
• Excellent output drive capability:
• Pin compatible with industry standard
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Inputs can be driven by 3.3V or 5V devices
• Multiple center pin and distributed Vcc/GND pins
• Packages available:
Logic Block Diagram
1
1
CLK
Balanced drives (24 mA sink and source)
Compatible with LVC
double-density pinouts
minimizing switching noise
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
– 48-pin 173 mil wide plastic TVSOP (K)
OE
1
D
0
TO 7 OTHER CHANNELS
TM
class of products.
D
C
1
O
0
1
Product Description
Pericom Semiconductor’s PI74FCT series of logic circuits are
produced in the Company’s advanced 0.6 micron CMOS tech-
nology, achieving industry leading speed grades.
The PI74FCT163374 is a 16-bit octal register designed with 16
D-type flip-flops with a buffered common clock and 3-state outputs.
The Output Enable (xOE) and clock (xCLK) controls are organized
to operate as two 8-bit registers or one 16-bit register. When OE is
HIGH, the outputs are in the high-impedance state. Input data
meeting the setup and hold time requirements of the D inputs is
transferred to the O outputs on the LOW-to-HIGH transition of the
clock input.
2
2
CLK
OE
2
D
0
3.3V 16-BIT REGISTER (3-STATE)
TO 7 OTHER CHANNELS
D
16-Bit Register (3-State)
C
PI74FCT163374
Fast CMOS 3.3V
PI74FCT163374
PS2056B
01/18/99
2
O
0